ISP1583BS ST-Ericsson Inc, ISP1583BS Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/6/627/st-ericsson_inc_sml.jpg)
ISP1583BS
Manufacturer Part Number
ISP1583BS
Description
IC USB CTRL HI-SPEED 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1583BSUM.pdf
(100 pages)
Specifications of ISP1583BS
Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1583BS
Manufacturer:
IDT
Quantity:
1 200
Company:
Part Number:
ISP1583BS
Manufacturer:
PHILPS
Quantity:
1 288
Part Number:
ISP1583BS
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
MICRON
Quantity:
2 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
ST-ERICS
Quantity:
829
Part Number:
ISP1583BSUM
Manufacturer:
STE
Quantity:
20 000
NXP Semiconductors
ISP1583_7
Product data sheet
8.2 Hi-Speed USB transceiver
8.3 MMU and integrated RAM
8.4 Microcontroller interface and microcontroller handler
8.5 OTG SRP module
The analog transceiver directly interfaces to the USB cable through integrated termination
resistors. The high-speed transceiver requires an external resistor (12.0 k
between pin RREF and ground to ensure an accurate current mirror that generates the
Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the
ISP1583 compliant to Hi-Speed USB and Original USB, supporting both the high-speed
and full-speed physical layers. After automatic speed detection, the NXP Serial Interface
Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling.
The Memory Management Unit (MMU) manages the access to the integrated RAM that is
shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is
stored in the integrated RAM, which is cleared only when the microcontroller has read the
corresponding endpoint, or the DMA controller has written all data from the RAM of the
corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly
cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is
available for buffering.
The microcontroller interface allows direct interfacing to most microcontrollers and
microprocessors. The interface is configured at power-up through pins BUS_CONF/DA0,
MODE1 and MODE0/DA1.
When pin BUS_CONF/DA0 = HIGH, the microcontroller interface switches to generic
processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate
16-bit data bus. If pin BUS_CONF/DA0 = LOW, the interface is in split bus mode, where
AD[7:0] is the local microprocessor bus (multiplexed address and data) and DATA[15:0] is
solely used as the DMA bus.
When pin MODE0/DA1 = HIGH, pins RW_N/RD_N and DS_N/WR_N are the read and
write strobes (8051 mode). If pin MODE0/DA1 = LOW, pins RW_N/RD_N and
DS_N/WR_N represent the direction and data strobes (Freescale mode).
When pin MODE1 = LOW, pin ALE/A0 is used to latch the multiplexed address on pins
AD[7:0]. When pin MODE1 = HIGH, pin ALE/A0 is used to indicate address or data. Pin
MODE1 is only used in split bus mode; in generic processor mode, it must be tied to
V
The microcontroller handler allows the external microcontroller to access the register set
in the NXP SIE, as well as the DMA handler. The initialization of the DMA configuration is
done through the microcontroller handler.
The OTG supplement defines a Session Request Protocol (SRP), which allows a B-device
to request the A-device to turn on V
A-device, which may be battery-powered, to conserve power by turning off V
there is no bus activity while still providing a means for the B-device to initiate bus activity.
Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a
standard USB peripheral, can initiate SRP.
CC(I/O)
.
Rev. 07 — 22 September 2008
BUS
and start a session. This protocol allows the
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
ISP1583
BUS
1 %)
when
14 of 99