Z16C3220VSG Zilog, Z16C3220VSG Datasheet - Page 16

• Manufacturer Part Number: Z16C3220VSG
• Description: IC Z16C32 MCU 20MHZ IUSC 68PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3220VSG

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4689-5; Z16C3220VSG

Transparent Bisync Mode. In this mode, the synchroni-
zation pattern is DLE-SYN, programmable selected from
either ASCII or EBCDIC encoding. The receiver recog-
nizes control character sequences and automatically
handles CRC calculations without CPU intervention. The
transmitter is programmed to send either SYN, DLE-SYN,
CRC-SYN, or CRC-DLE-SYN upon underrun and automati-
cally sends the closing DLE-SYN with optional CRC at the
end of a programmed message length.
External Sync Mode. The receiver is synchronized to the
receive data by an externally-supplied signal on a pin for
custom protocol applications.
Data Encoding
The IUSC is programmed to encode and decode the serial
data in any of eight different ways (Figure 6). The transmit-
ter encoding method is selected independently of the
receiver decoding method.
NRZ. In NRZ, a 1 is represented by a High level for the
duration of the bit cell and a 0 is represented by a Low level
for the duration of the bit cell.
NRZB. NRZB is inverted from NRZ.
NRZI-Mark. In NRZI-Mark, a 1 is represented by a transi-
tion at the beginning of a bit cell, i.e., the level present in the
preceding bit cell is reversed. A 0 is represented by the
absence of a transition at the beginning of the bit cell.
Z
PS97USC0200
ILOG
DIFFERENTIAL
BI-PHASE-M
BIPHASE-S
BIPHASE-L
BIPHASE-L
NRZI-M
NRZI-S
NRZB
Data
NRZ
1
1
P R E L I M I N A R Y
Figure 6. Data Encoding
0
NRZI-Space. In NRZI-Space, a 1 is represented by the
absence of a transition at the beginning of a bit cell, i.e., the
level present in the preceding bit cell is maintained. A 0 is
represented by a transition at the beginning of the bit cell.
Biphase-Mark. In Biphase-Mark, a 1 is represented by a
transition at the beginning of the bit cell and another
transition at the center of the bit cell. A 0 is represented by
a transition at the beginning of the bit cell only.
Biphase-Space. In Biphase-Space, a 1 is represented by
a transition at the beginning of the bit cell only. A 0 is
represented by a transition at the beginning of the bit cell
and another transition at the center of the bit cell.
Biphase-Level. In Biphase-Level, a 1 is represented by a
High during the first half of the bit cell and a Low during the
second half of the bit cell. A 0 is represented by a Low
during the first half of the bit cell and a High during the
second half of the bit cell.
Differential Biphase-Level. In Differential Biphase-Level,
a 1 is represented by a transition at the center of the bit cell,
with the opposite polarity from the transition at the center
of the preceding bit cell. A 0 is represented by a transition
at the center of the bit cell with the same polarity as the
transition at the center of the preceding bit cell. In both
cases, there are transitions at the beginning of the bit cell
to set up the level required to make the correct center
transition.
0
1
0
Z16C32 IUSC
16
™