Z16C3220VSG Zilog, Z16C3220VSG Datasheet - Page 115

• Manufacturer Part Number: Z16C3220VSG
• Description: IC Z16C32 MCU 20MHZ IUSC 68PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3220VSG

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4689-5; Z16C3220VSG

AC CHARACTERISTICS (Continued)
Timing Table
115
Z
ILOG
No
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121a
121b
122a
122b
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
Symbol
TsIEI(PIA)
ThIEI(PIA)
TdPIA(IEO)
TdPIA(INT)
TdPIAf(RDY)
TdPIAr(RDY)
TdPIA(Wf)
TdPIA(Wr)
TdSIA(INT)
TwSTBh
TwRESl
TwRESh
TdRES(STB)
TdDSf(RDY)
TdWRf(RDY)
TdWRr(RDY)
TdRDf(RDY)
TwCLKl
TwCLKh
TwCLKh
TcCLK
TcCLK
TfCLK
TrCLK
TdCLKr (UAS)
TwUASl
TdCLKf(UAS)
TdCLKr(AS)
TwASl
TdCLKf(AS)
TdAS(DSr)
TdCLKr(DS)
TwDSlr
TdCLKf(DS)
TsDR(DS)
ThDR(DS)
TdCLK(RW)
TdAS(RD)
TdCLKr(RD)
TwRDl
TdCLKf(RD)
TsDR(RD)
ThDR(RD)
TdCLK(ADD)
TdCLK(AD)
ThAD(PC)
IEI to Pulsed /INTACK Fall Setup Time
IEI to Pulsed /INTACK Rise Hold Time
Pulsed /INTACK Fall to IEO Delay
Pulsed /INTACK Fall to /INT Inactive Delay
Pulsed /INTACK Fall to /WAIT Fall Delay
Pulsed /INTACK Fall to /WAIT Rise Delay
Status /INTACK Fall to IEO Inactive Delay
/RESET Low Width
/RESET Rise to /STB Fall
/DS Fall to /RDY Fall Delay
/RD Fall to /RDY Fall Delay
CLK Low Width
CLK High Width
CLK High Width (Linked List Mode)
CLK Fall Time
CLK Rise Time
/UAS Low Width
CLK Fall to /UAS Rise Delay
CLK Rise to /AS Fall Delay
/AS Low Width
CLK Fall to /AS Rise Delay
CLK Rise to /DS Delay
/DS (Read) Low Width
CLK Fall to /DS Delay
Read Data to /DS Rise Setup Time
Read Data to /DS Rise Hold Time
CLK Rise to R//W Delay
/AS Rise to /RD Fall Delay
CLK Rise to /RD Delay
/RD Low Width
CLK Fall to /RD Delay
Read Data to /RD Rise Setup Time
Read Data to /RD Rise Hold Time
CLK Rise to Direct Address Delay
Address to CLK Rise Hold Time
Parameter
Pulsed /INTACK Fall to /RDY Fall Delay
Pulsed /INTACK Rise to /RDY Rise Delay
/Strobe High Width
/RESET High Width
/WR Fall to /RDY Fall Delay
/WR Rise to /RDY Rise Delay
CLK Cycle Time
CLK Cycle Time (Linked List Mode)
CLK Rise to /UAS Fall Delay
/AS Rise to /DS Fall (Read) Delay
CLK Rise to Address Delay
P R E L I M I N A R Y
TdCLKf(DS)
Min
170
10
50
60
60
25
25
35
50
60
25
25
25
75
30
25
75
30
0
0
0
0
Max
200
200
200
200
60
40
40
50
50
40
50
30
30
30
30
30
30
30
30
30
30
35
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PS97USC0200
Z16C32 IUSC
[6,7,13]
[6,7,13]
[6,9,13]
Note
[6,8]
[6,8]
[6,9]
[1,6]
[12]
[12]
[2]
[3]
[3]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
™