LAN9118-MT SMSC, LAN9118-MT Datasheet - Page 117

• Manufacturer Part Number: LAN9118-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1013

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.2
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
asu
don
doff
doh
csh
nCS, nRD
csl
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 LAN9118 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
117
MIN
45
32
13
0
0
0
0
TYP
Revision 1.5 (07-11-08)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns