LAN9210-ABZJ SMSC, LAN9210-ABZJ Datasheet - Page 58

• Manufacturer Part Number: LAN9210-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC

Specifications of LAN9210-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1048-6

Revision 2.7 (03-15-10)
3.12.6.3
TX Example 3
In this example a single, 111-Byte Ethernet packet will be transmitted with a TX checksum. This packet
is divided into four buffers. The four buffers are as follows:
Buffer 0:
Buffer 1:
Buffer 2:
Buffer 3:
Figure 3.15, "TX Example 1"
how data is passed to the TX data FIFO.
Note: In order to perform a TX checksum calculation on the associated packet, bit 14 (CK) of the TX
4-Byte “Data Start Offset”
4-Byte Checksum Preamble
16-Byte “Buffer End Alignment”
7-Byte “Data Start Offset”
79-Bytes of payload data
16-Byte “Buffer End Alignment”
0-Byte “Data Start Offset”
15-Bytes of payload data
16-Byte “Buffer End Alignment”
10-Byte “Data Start Offset”
17-Bytes of payload data
16-Byte “Buffer End Alignment”
Command ‘B’ must be set in conjunction with bit 13 (FS) of TX Command ‘A’ and bit 16
(TXCOE_EN) of the COE_CR register. For more information, refer to
Checksum Offload Engine
illustrates the TX command structure for this example, and also shows
(TXCOE)".
DATASHEET
58
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Section 3.6.2, "Transmit
SMSC LAN9210
Datasheet