SJA1000T/N1,118 NXP Semiconductors, SJA1000T/N1,118 Datasheet - Page 42

• Manufacturer Part Number: SJA1000T/N1,118
• Description: IC STAND-ALONE CAN CTRLR 28-SOIC
• Manufacturer: NXP Semiconductors

Specifications of SJA1000T/N1,118

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: CAN
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Frequency: 24 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 15 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package: 28SO
• Maximum Data Rate: 1 Mbps
• Minimum Single Supply Voltage: 4.5 V
• Standard Supported: CAN 2.0B
• Power Down Mode: Sleep
• Maximum Single Supply Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1123-2; 935230920118; SJA1000TD-T

Philips Semiconductors
The lower the binary value of the identifier the higher the
priority. This is due to the larger number of leading
dominant bits during arbitration.
6.4.13.5
The number of transferred data bytes is defined by the
data length code. The first bit transmitted is the most
significant bit of data byte 1 at CAN address 19 (SFF) or
CAN address 21 (EFF).
6.4.14.1
The bit layout of the receive buffer is represented in Tables 34 to 36 for SFF and Tables 37 to 41 for EFF. The given
configuration is chosen to be compatible with the transmit buffer layout (see Section 6.4.13.2).
Table 34 RX frame information (SFF); CAN address 16
Notes
1. Frame format.
2. Remote transmission request.
3. Data length code bit.
2000 Jan 04
handbook, full pagewidth
Stand-alone CAN controller
Message 1 is now available in the receive buffer.
BIT 7
FF
(1)
Data field
Descriptor field of the receive buffer
RTR
BIT 6
(2)
messages
Fig.8 Example of the message storage within the RXFIFO.
incoming
BIT 5
0
command
64-byte
release
receive
buffer
BIT 4
FIFO
0
42
6.4.14
The global layout of the receive buffer is very similar to the
transmit buffer described in the previous section.
The receive buffer is the accessible part of the RXFIFO
and is located in the range between CAN address
16 and 28. Each message is subdivided into a descriptor
and a data field.
message 3
message 2
message 1
DLC.3
BIT 3
(3)
R
ECEIVE BUFFER
28
27
26
25
24
23
22
21
20
19
18
17
16
DLC.2
CAN address
BIT 2
window
receive
buffer
MGK622
(3)
DLC.1
BIT 1
Product specification
(3)
SJA1000
DLC.0
BIT 0
(3)