KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 72

• Manufacturer Part Number: KSZ8873MLL
• Description: IC ETHERNET SWITCH 3PORT 64-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873MLL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• No. Of Ports: 3
• Ethernet Type: IEEE 802.3u
• Supply Current: 115mA
• Supply Voltage Range: 2.5V, 3.3V
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (15-Dec-2010)
• Base: RoHS Compliant
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Interface Type: MII, RMII
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3459

Micrel, Inc.
Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8873 and the external processor.
Register 118 (0x76): User Defined Register 1
Register 119 (0x77): User Defined Register 2
Register 120 (0x78): User Defined Register 3
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address
table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Register 122 (0x7A): Indirect Access Control 1
Note: A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
Register 124 (0x7C): Indirect Data Register 7
September 2010
Bit
7-0
Bit
7-0
Bit
7-0
Bit
7-5
4
3-2
1-0
Bit
7-0
Bit
7
6-3
2-0
Bit
7-0
UDR1
UDR2
UDR3
Read High /
Write Low
Indirect
Address High
Indirect
Address Low
CPU Read
Status
Indirect Data
[66:64]
Indirect Data
[63:56]
Name
Name
Name
Name
Reserved
Table Select
Name
Name
Reserved
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
R/W
R/W
Description
Description
Description
Description
Reserved
Do not change the default values.
=1, Read cycle
=0, Write cycle
=00, Static MAC address table selected
=01, VLAN table selected
=10, Dynamic MAC address table selected
=11, MIB counter selected
Bits [9:8] of indirect address
Description
Bits [7:0] of indirect address
Description
This bit is applicable only for dynamic MAC address table
and MIB counter reads.
=1, Read is still in progress
=0, Read has completed
Reserved
Bits [66:64] of indirect data
Description
Bits [63:56] of indirect data
72
Default
0x00
Default
0x00
Default
0x00
Default
000
0
00
00
Default
0000_0000
Default
0
0000
000
Default
0000_0000
KSZ8873MLL/FLL/RLL
M9999-092309-1.2