KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 56
![IC ETHERNET SWITCH 3PORT 64-LQFP](/photos/6/81/68149/64-lqfp-micrel_sml.jpg)
KSZ8873MLL
Manufacturer Part Number
KSZ8873MLL
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL
Data Rate
100Mbps
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Ports
3
Ethernet Type
IEEE 802.3u
Supply Current
115mA
Supply Voltage Range
2.5V, 3.3V
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (15-Dec-2010)
Base
RoHS Compliant
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Temperature Classification
Commercial
Interface Type
MII, RMII
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-3459
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8873MLL
Manufacturer:
Micrel Inc
Quantity:
1 934
Company:
Part Number:
KSZ8873MLL
Manufacturer:
ADI
Quantity:
27
Company:
Part Number:
KSZ8873MLL AM
Manufacturer:
Micrel
Quantity:
1 638
Company:
Part Number:
KSZ8873MLLJ
Manufacturer:
Micrel
Quantity:
323
Micrel, Inc.
Port Registers (Registers 16 – 95)
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are
the same for all ports, but the address for each port is different, as indicated.
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
September 2010
Bit
7
6
5
4-3
2
1
0
Broadcast
Storm
Protection
Enable
DiffServ
Priority
Classification
Enable
802.1p
Priority
Classification
Enable
Port-based
Priority
Classification
Tag Insertion
Tag
Removal
TXQ Split
Enable
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
=1, Enable broadcast storm protection for ingress packets on port
=0, Disable broadcast storm protection
=1, Enable DiffServ priority classification for ingress packets (IPv4) on
port
=0, Disable DiffServ function
=1, Enable 802.1p priority classification for ingress packets on port
=0, Disable 802.1p
=00, Ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=01, Ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=10, Ingress packets on port will be
classified as priority 2 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
=11, Ingress packets on port will be
classified as priority 3 queue if “Diffserv” or “802.1p” classification is not
enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be enabled at the same
time. The OR’ed result of 802.1p and DSCP overwrites the port priority.
=1, When packets are output on the port, the switch will add 802.1p/q
tags to packets without 802.1p/q tags when received. The switch will not
add tags to packets already tagged. The tag inserted is the ingress
port’s “port VID”.
=0, Disable tag insertion
=1, When packets are output on the port, the switch will remove
802.1p/q tags from packets with 802.1p/q tags when received. The
switch will not modify packets received without tags.
=0, Disable tag removal
=1, Split TXQ to 4 queue configuration. It cannot be enable at the same
time with split 2 queue at register 18, 34,50 bit 7.
=0, No split, treated as 1 queue configuration
56
KSZ8873MLL/FLL/RLL
Default
0
0
0
00
0
0
0
M9999-092309-1.2