CY7C63801-PXC Cypress Semiconductor Corp, CY7C63801-PXC Datasheet - Page 60

• Manufacturer Part Number: CY7C63801-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63801-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

21.3 Endpoint 0 Mode
Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers, the SIE provides an interlocking
mechanism to prevent accidental overwriting of data.
When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to
this register clears the upper four bits regardless of the value written.
Table 21-3. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Document 38-08035 Rev. *N
Note
Bit 7: SETUP Received
This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet phase of
the SETUP transactions until the end of the data phase of a control write transfer, and cannot be cleared during this interval.
While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
This bit is cleared by any nonlocked writes to the register.
0 = No SETUP received
1 = SETUP received
Bit 6: IN Received
This bit when set indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowledges an IN data
packet. When clear, it indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK
handshake.
This bit is cleared by any nonlocked writes to the register.
0 = No IN received
1 = IN received
Bit 5: OUT Received
This bit when set indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last received
packet in an OUT transaction. When clear, it indicates no OUT received.
This bit is cleared by any nonlocked writes to the register.
0 = No OUT received
1 = OUT received
Bit 4: ACK’d Transaction
The ACK’d transaction bit is set when the SIE engages in a transaction to the register’s endpoint, which completes with a ACK
packet.
This bit is cleared by any nonlocked writes to the register.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode [3:0]
The endpoint modes determine how the SIE responds to the USB traffic that the host sends to the endpoint. The mode controls
how the USB SIE responds to traffic, and how the USB SIE changes the mode of that endpoint as a result of host packets to the
endpoint.
5. C = Clear. This bit is cleared only by the user and cannot be set by firmware.
Read/Write
Default
Field
Bit #
Setup Received
R/C
7
0
[5]
IN Received
R/C
6
0
[5]
OUT Received
R/C
5
0
[5]
ACK’d Trans
R/C
4
0
[5]
R/W
3
0
R/W
CY7C63310, CY7C638xx
2
0
Mode[3:0]
R/W
1
0
Page 60 of 86
R/W
0
0
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