CY7C63801-PXC Cypress Semiconductor Corp, CY7C63801-PXC Datasheet - Page 41

• Manufacturer Part Number: CY7C63801-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63801-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 14-13. P3 Configuration (P3CR) [0x16] [R/W]
15. Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, so that its functionality is independent of system clock speed.
SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
15.1 SPI Data Register
Table 15-1. SPI Data Register (SPIDATA) [0x3C] [R/W]
When an interrupt occurs to indicate to the firmware that a byte of receive data is available, or the transmitter holding register is empty,
the firmware has 7 SPI clocks to manage the buffers: to empty the receiver buffer or to refill the transmit holding register. Failure to
meet this timing requirement results in incorrect data transfer.
Document 38-08035 Rev. *N
This register exists in CY7C638(2/3)3. This register controls the operation of pins P3.0–P3.1.
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.
Bit [7:0]: SPI Data [7:0]
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
Reserved
R/W
7
–
0
7
0
Int Enable
R/W
R/W
6
0
6
0
Int Act Low
R/W
R/W
5
0
5
0
TTL Thresh
R/W
R/W
4
0
4
0
SPIData[7:0]
Reserved
R/W
3
–
0
3
0
Open Drain
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
Pull-up Enable
R/W
R/W
1
1
1
0
Output Enable
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R/W
R/W
0
0
0
0
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