CS8900A-IQ3Z Cirrus Logic Inc, CS8900A-IQ3Z Datasheet - Page 46
![IC LAN ETHERNET CTLR 3V 100LQFP](/photos/6/81/68139/cs8900a-iq3z_sml.jpg)
CS8900A-IQ3Z
Manufacturer Part Number
CS8900A-IQ3Z
Description
IC LAN ETHERNET CTLR 3V 100LQFP
Manufacturer
Cirrus Logic Inc
Type
Single Chipr
Specifications of CS8900A-IQ3Z
Package / Case
100-LQFP
Controller Type
Ethernet Controller (IEEE 802.3)
Interface
ISA-BUS
Voltage - Supply
3V, 5V
Current - Supply
95mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Ethernet Connection Type
10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Supply Voltage (max)
6 V
Supply Voltage (min)
- 0.3 V
Supply Current (max)
+/- 10 mA
Maximum Operating Temperature
+ 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1163 - KIT EVAL FOR CS8900A
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1129
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
1 852
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
CIRRUS42
Quantity:
921
Company:
Part Number:
CS8900A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS8900A-IQ3Z
Manufacturer:
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Quantity:
20 000
Company:
Part Number:
CS8900A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Reset value is: 0000 0000 0000 0000
4.3.6 DMA Frame Count
(Read only, Address: PacketPage base + 0028h)
The lower 12 bits of the DMA Frame Count register define the number of valid frames transferred via DMA since the
last readout of this register. The upper 4 bits are reserved. See Section 5.3 on page 90.
Reset value is: XXXX 0000 0000 0000
4.3.7 RxDMA Byte Count
(Read only, Address: PacketPage base + 002Ah)
The RxDMA Byte Count register describes the valid number of bytes DMAed since the last readout. See Section 5.3
on page 90.
Reset value is: 0000 0000 0000 0000
4.3.8 Memory Base Address
(Read/Write, Address: PacketPage base + 002Ch)
Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base
address. The upper three nibbles are reserved.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000
4.3.9 Boot PROM Base Address
(Read/Write, Address: PacketPage base + 0030h)
46
Address 002Fh
Address 0033h
Reserved
Reserved
Most significant byte of frame count
Most significant byte of byte count
(most-significant nibble always 0h)
Address 002Bh
Address 0029h
The most significant nibble of
high-order nibble is reserved.
The most significant nibble of
memory base address. The
Boot PROM base address.
The high-order nibble is
CIRRUS LOGIC PRODUCT DATASHEET
Address 002Eh
Address 0032h
reserved.
Contains portion of Boot PROM
Contains portion of memory
Address 002Dh
Address 0031h
base address.
base address.
Least significant byte of frame count
Least significant byte of byte count
Crystal LAN™ Ethernet Controller
Address 002Ah
Address 0028h
The least significant byte of
The least significant byte of
the memory base address.
the Boot PROM base
Address 002Ch
Address 0030h
address.
CS8900A
DS271F5