PCA9564D,112 NXP Semiconductors, PCA9564D,112 Datasheet - Page 7

• Manufacturer Part Number: PCA9564D,112
• Description: IC CTRL PARALLEL/I2C BUS 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9564D,112

• Controller Type: Parallel Bus to I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 6mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: 568-4001 - DEMO BOARD FOR PCA9564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1062-5; 935272894112; PCA9564D

Philips Semiconductors
More Information on SIO Operating Modes
The four operating modes are:
– Master Transmitter
– Master Receiver
– Slave Receiver
– Slave Transmitter
Data transfers in each mode of operation are shown in Figures 2–5.
These figures contain the following abbreviations:
Abbreviation
S
SLA
R
W
A
A
Data
P
In Figures 2-5, circles are used to indicate when the serial interrupt
flag is set. A serial interrupt is not generated when I2CSTA = F8H.
This happens on a stop condition. The numbers in the circles show
the status code held in the I2CSTA register. At these points, a service
routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is
suspended until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2CSTA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 2-6.
Master Transmitter Mode: In the master transmitter mode, a
number of data bytes are transmitted to a slave receiver (see
Figure 2). Before the master transmitter mode can be entered,
I2CCON must be initialized as follows:
ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset,
SIO will not acknowledge its own slave address in the event of
another device becoming master of the bus. In other words, if AA is
reset, SIO cannot enter a slave mode. STA, STO, and SI must be
reset.
The master transmitter mode may now be entered by setting the
STA bit. The SIO logic will now test the I
condition as soon as the bus becomes free. When a START
condition is transmitted, the serial interrupt flag (SI) is set, and the
status code in the status register (I2CSTA) will be 08H. This status
code must be used to vector to an interrupt service routine that
loads I2CDAT with the slave address and the data direction bit
(SLA+W). The SI bit in I2CCON must then be reset before the serial
transfer can continue.
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in I2CSTA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status codes is
detailed in Table 2. After a repeated start condition (state 10H). SIO
may switch to the master receiver mode by loading I2CDAT with
SLA+R).
Note that a master should never transmit its own slave
address.
2006 Sep 01
I2CCON
Parallel bus to I
AA
X
7
ENSIO
Explanation
Start condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Acknowledge bit (LOW level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
Stop condition
6
1
STA
2
5
0
C-bus controller
STO
4
0
2
C-bus and generate a start
SI
0
3
CR2
2
bit rate
CR1
1
CR0
0
7
Master Receiver Mode: In the master receiver mode, a number of
data bytes are received from a slave transmitter (see Figure 3). The
transfer is initialized as in the master transmitter mode. When the
start condition has been transmitted, the interrupt service routine
must load I2CDAT with the 7-bit slave address and the data
direction bit (SLA+R). The SI bit in I2CCON must then be cleared
before the serial transfer can continue.
When the slave address and the data direction bit have been
transmitted and an acknowledgment bit has been received, the
serial interrupt flag (SI) is set again, and a number of status codes in
I2CSTA are possible. These are 40H, 48H, or 38H for the master
mode and also 68H, or B0H if the slave mode was enabled (AA =
logic 1). The appropriate action to be taken for each of these status
codes is detailed in Table 3. ENSIO is not affected by the serial
transfer and are not referred to in Table 3. After a repeated start
condition (state 10H), SIO may switch to the master transmitter
mode by loading I2CDAT with SLA+W.
Note that a master should not transmit its own slave address.
Slave Receiver Mode: In the slave receiver mode, a number of
data bytes are received from a master transmitter (see Figure 4). To
initiate the slave receiver mode, I2CADR and I2CCON must be
loaded as follows:
The upper 7 bits are the address to which SIO will respond when
addressed by a master.
ENSIO must be set to logic 1 to enable SIO. The AA bit must be set
to enable SIO to acknowledge its own slave address, STA, STO,
and SI must be reset.
When I2CADR and I2CCON have been initialized, SIO waits until it
is addressed by its own slave address followed by the data direction
bit which must be “0” (W) for SIO to operate in the slave receiver
mode. After its own slave address and the W bit have been
received, the serial interrupt flag (I) is set and a valid status code
can be read from I2CSTA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 4. The slave receiver
mode may also be entered if arbitration is lost while SIO is in the
master mode (see status 68H).
If the AA bit is reset during a transfer, SIO will return a not
acknowledge (logic 1) to SDA after the next received data byte.
While AA is reset, SIO does not respond to its own slave address.
However, the I
be resumed at any time by setting AA. This means that the AA bit
may be used to temporarily isolate SIO from the I
I2CCON
I2CADR
BIT7
AA
2
7
1
7
C-bus is still monitored and address recognition may
BIT6
ENSIO
6
1
6
BIT5
5
STA
own slave address
5
0
BIT4
4
STO
4
0
BIT3
3
SI
0
3
BIT2
PCA9564
CR2
2
Product data sheet
2
2
X
C-bus.
CR1
BIT1
X
1
1
0
CR0
0
X
0