MAX9856ETL+T Maxim Integrated Products, MAX9856ETL+T Datasheet - Page 39

• Manufacturer Part Number: MAX9856ETL+T
• Description: IC AUDIO CODEC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+T

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX9856 has comprehensive power management
that allows unused features to be disabled, thereby
The MAX9856 features an I
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facil-
itate communication between the MAX9856 and the
master at clock rates up to 400kHz. Figure 8 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9856 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9856 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9856 transmits the proper slave address
Table 16. Power-Management Register
Power-Management Register Bit Description
Figure 8. 2-Wire Interface Timing Diagram
SMBus is a trademark of Intel Corp.
SDA
SCL
REGISTER
0x1C
t
HD, STA
CONDITION
LOUTEN
DAREN
ADREN
DALEN
ADLEN
START
DIGEN
SHDN
BITS
Power Management and Control
______________________________________________________________________________________
SHDN
B7
t
LOW
t
R
2
t
t
SU, DAT
HIGH
I
C/SMBus™-compatible,
2
Shutdown. Overrides all settings and forces the entire device into a shutdown state.
Digital Core Enable. Set high to use either the DAC or ADC.
Line Output Enable.
Left DAC Enable.
Right DAC Enable.
Left ADC Enable.
Right ADC Enable.
C Serial Interface
DirectDrive Headphone Amplifiers
B6
0
t
F
t
HD, DAT
Low-Power Audio CODEC with
DIGEN
B5
t
HD, STA
LOUTEN
START CONDITION
B4
saving power. Table 16 shows the power/management
register and a register bit description.
followed by a series of nine SCL pulses. The MAX9856
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowl-
edge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typi-
cally greater than 500Ω, is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically
greater than 500Ω, is required on SCL if there are mul-
tiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with
SDA and SCL are optional. Series resistors protect the
digital inputs of the MAX9856 from high voltage spikes
on the bus lines, and minimize crosstalk and under-
shoot of the bus signals.
REPEATED
FUNCTION
t
DALEN
HD, STA
B3
DAREN
t
B2
SP
t
SU, STO
ADLEN
CONDITION
B1
STOP
t
BUF
CONDITION
START
ADREN
B0
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