MAX9856ETL+T Maxim Integrated Products, MAX9856ETL+T Datasheet - Page 21

• Manufacturer Part Number: MAX9856ETL+T
• Description: IC AUDIO CODEC 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+T

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading status register 0x00. If a
flag is set, it is reported as a hardware interrupt only if
The MAX9856 can work with a master clock supplied
from any system clock (MCLK) within the range of
10MHz to 60MHz range. A clock prescaler divides by
1, 2, or 4 to create an internal clock (PCLK) in the
10MHz to 20MHz range.
There are two clock-generation circuits that operate
independently for the ADC and DAC path, allowing the
ADC and DAC to be operated at different sample rates.
BCLK services the LRCLK signals for both the ADC and
Table 3. Interrupt Enable Bit Locations
Table 4. Clock Control Register
Clock Control Register Bit Description
REG
0x03
PSCLK
REG
0x02
BSEL
BITS
MAS
MCLK Prescaler. Set PSCLK to appropriately divide down MCLK to a usable frequency:
000—Disable clock input
001—10MHz ≤ MCLK ≤ 16MHz (PCLK = MCLK/1)
010—16MHz ≤ MCLK ≤ 20MHz (PCLK = MCLK/1)
011—20MHz ≤ MCLK ≤ 32MHz (PCLK = MCLK/2)
100—32MHz ≤ MCLK ≤ 40MHz (PCLK = MCLK/2)
101—40MHz ≤ MCLK ≤ 60MHz (PCLK = MCLK/4)
110—Reserved
111—Reserved
Master Mode. Selects between master and slave operation:
0 = Slave mode (BCLK, LRCLK_D, and LRCLK_A are inputs)
1 = Master mode (BCLK, LRCLK_D, and LRCLK_A are outputs)
BCLK Select. Configures BCLK when operating in master mode. Set BSEL to be a sufficiently high frequency to
fully clock in all data bits for both the DAC and ADC, if operating at different sample rates:
000—Off
001—Off
010—BCLK = 48 x LRCLK_D (recommended if the DAC and ADC operate at the same rate)
011—BCLK = 48 x LRCLK_A
100—BCLK = PCLK/2 (recommended if the DAC and ADC are not operating at the same rate)
101—BCLK = PCLK/4
110—BCLK = PCLK/8
111—BCLK = PCLK/16
ICLD
B7
B7
______________________________________________________________________________________
0
ISLD
B6
B6
Interrupt Enables
DirectDrive Headphone Amplifiers
Clock Control
PSCLK
Low-Power Audio CODEC with
IULK
B5
B5
B4
B4
0
FUNCTION
the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective bit
location in register 0x00. Table 3 lists the interrupt enable
bit locations and description.
DAC. When the ADC and DAC operate at different
LRCLK rates, BCLK should be set appropriately for the
higher sample rate. The number of clock cycles per
frame must be greater than or equal to the configured
bit depth.
The MAX9856 digital audio interface can operate in
either master or slave mode. In master mode, the
MAX9856 generates the BCLK and LRCLK signals,
which control the data flow on the digital audio inter-
face. In slave mode, the external master device gener-
ates the BCLK and LRCLK signals. See Table 4.
IHPOCL
MAS
B3
B3
IHPOCR
B2
B2
BSEL
IJDET
B1
B1
IGPI
B0
B0
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