MAX9867EWV+T Maxim Integrated Products, MAX9867EWV+T Datasheet - Page 46

• Manufacturer Part Number: MAX9867EWV+T
• Description: IC STEREO AUD CODEC LP 30WLP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867EWV+T

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-WLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX9867EWV+T; MAX9867EWV+TTR

Ultra-Low Power Stereo Audio Codec
The MAX9867 features an I
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9867 and the mas-
ter at clock rates up to 400kHz. Figure 9 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9867 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each word transmitted to
the MAX9867 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9867 transmits the proper slave address
followed by a series of nine SCL pulses. The MAX9867
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω is required on SDA. SCL operates only as an
input. A pullup resistor, typically greater than 500Ω, is
Figure 9. 2-Wire Interface Timing Diagram
Figure 10. START, STOP, and REPEATED START Conditions
46
______________________________________________________________________________________
SDA
SCL
t
HD, STA
START CONDITION
t
LOW
SDA
SCL
t
R
t
I
2
SU, DAT
t
2
HIGH
C/SMBus-compatible,
C Serial Interface
t
F
S
t
HD, DAT
t
SU, STA
REPEATED START CONDITION
Sr
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9867 from high-voltage spikes on the bus lines, and
minimize crosstalk, and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals. See the START and STOP
Conditions section.
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 10). A START
condition from the master signals the beginning of a
transmission to the MAX9867. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
t
HD, STA
P
t
SP
START and STOP Conditions
t
SU, STO
CONDITION
STOP
t
BUF
CONDITION
Bit Transfer
START