MAX9867EWV+T Maxim Integrated Products, MAX9867EWV+T Datasheet - Page 21

• Manufacturer Part Number: MAX9867EWV+T
• Description: IC STEREO AUD CODEC LP 30WLP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867EWV+T

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-WLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX9867EWV+T; MAX9867EWV+TTR

The MAX9867 is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
The stereo playback path accepts digital audio through
a flexible interface compatible with I
justified signals. An oversampling sigma-delta DAC
converts the incoming digital data stream to analog
audio and outputs the audio through the stereo head-
phone amplifier. The headphone amplifier can be con-
figured in differential, single-ended, and capacitorless
output modes.
The stereo record path has two analog microphone
inputs with selectable gain. An integrated microphone
bias can be used to power the microphones. The left
analog microphone inputs can also accept data from
up to two digital microphones. An oversampling sigma-
delta ADC converts the microphone signals and out-
puts the digital bit stream over the digital audio
interface.
Integrated digital filtering provides a range of notch and
highpass filters for both the playback and record paths
to limit undesirable low-frequency signals and GSM
TQFN-EP
24, 25
22
23
26
27
28
29
30
31
32
—
PIN/BUMP
WLP
______________________________________________________________________________________
D1
C2
C1
E3
E2
E1
B1
B2
A1
—
—
Detailed Description
Ultra-Low Power Stereo Audio Codec
DVDDIO
SDOUT
LOUTP
LRCLK
NAME
MCLK
DVDD
PVDD
BCLK
SDIN
N.C.
EP
2
S, TDM, and left-
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
No Connection
Digital Audio Interface Power Supply. Bypass to DGND with a 1µF capacitor.
Digital Audio Serial-Data ADC Output
Digital Audio Serial-Data DAC Input
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock
and determines whether the audio data on SDIN is routed to the left or right
channel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is an
input when the MAX9867 is in slave mode and an output when in master mode.
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is in
slave mode and an output when in master mode.
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
Digital Power Supply. Supply for the digital circuitry and I
DGND with a 1µF capacitor.
Exposed Pad. Connect the exposed thermal pad to AGND.
transmission noise. The digital filtering provides attenuation
of out-of-band energy by over 70dB, eliminating audi-
ble aliasing. A digital sidetone function allows audio
from the record path to be summed into the playback
path after digital filtering.
The MAX9867 also includes two stereo, single-ended
line inputs with gain adjustment, which can be record-
ed by the ADCs and/or output by the headphone ampli-
fiers. An auxiliary ADC accurately measures a DC
voltage by utilizing the right audio ADC and reporting
the DC voltage through the I
tion function allows the detection of headphone, micro-
phone, and headset jacks. Insertion and removal
events can be programmed to trigger a hardware inter-
rupt and flag an I
The MAX9867’s flexible clock circuitry utilizes a program-
mable clock divider and a digital PLL, allowing the DAC
and ADC to operate at maximum dynamic range for all
combinations of master clock (MCLK) and sample rate
(LRCLK) without consuming extra supply current. Any
master clock between 10MHz and 60MHz is supported
as are all sample rates from 8kHz to 48kHz. Master and
slave modes are supported for maximum flexibility.
Pin Description (continued)
FUNCTION
2
C register bit.
2
C interface. A jack detec-
2
C interface. Bypass to
21