max9867 Maxim Integrated Products, Inc., max9867 Datasheet
max9867
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max9867 Summary of contents
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... The MAX9867 operates from a single 1.8V supply, and supports a 1.65V to 3.6V logic level interface provides control for volume levels, signal mixing, and general operating modes. The MAX9867 is available in a tiny 2.2mm x 2.7mm, 0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mm TQFN package is also available. LINEIN 1 ...
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Ultra-Low Power Stereo Audio Codec ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, and PVDD .........................................-0.3V to +2V DVDDIO.................................................................-0.3V to +3.6V DGND and PGND..................................................-0.1V to +0.1V PREG, REF, REG, MICBIAS ....................-0.3V to (AVDD + 0.3V) MCLK, LRCLK, BCLK ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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Ultra-Low Power Stereo Audio Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD PVDD DVDD DVDDIO mode 2.2µ REF MICBIAS PREG 0dB, MCLK = 13MHz ...
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... SU, STO Bus Capacitance Pulse Width of Suppressed Spike Note 2: The MAX9867 is 100% production tested at T Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode. Note 4: DAC performance measured at the headphone outputs. Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS. ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted TOTAL HARMONIC DISTORTION + NOISE vs. POWER OUT ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (LINE ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MIC TO ADC) ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted FFT, DAC TO HEADPHONE, -60dBFS, MCLK = 13MHz, ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted DAC IIR HIGHPASS FILTER FREQUENCY RESPONSE, MODE = ...
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Ultra-Low Power Stereo Audio Codec ( +1.8V, C AVDD DVDD PVDD REF 8kHz 20Hz +25°C, unless otherwise noted FULL OPERATION TO SHUTDOWN (DAC) TIME (1ms/div) TOTAL ...
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Ultra-Low Power Stereo Audio Codec PIN/BUMP NAME TQFN-EP WLP 1 A2 DGND 2 B3 SCL 3 A3 SDA IRQ AVDD 6 B4 REF 7 A5 PREG 8 B5 REG 9 A6 AGND 10 B6 MICBIAS MICLN/ ...
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... SDIN is routed to the left or right channel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is an input when the MAX9867 is in slave mode and an output when in master mode. Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is in slave mode and an output when in master mode ...
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... Microphone MICCLK VSEN Mode DSLEW POWER MANAGEMENT SHDN System Shutdown LNLEN Revision 22 ______________________________________________________________________________________ 2 C Registers The MAX9867 responds to the slave address 0x30 for all write commands and 0x31 for all read operations ULK 0 0 JKMIC 0 0 AUX[15:8] AUX[7:0] SDODLY IULK ...
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Ultra-Low Power Stereo Audio Codec Status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. The status register bits are cleared upon reading the status Table 2. Status Registers REGISTER B7 Status (Read Only) ...
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... Internally, the MAX9867 requires a 10MHz-to-20MHz clock. A prescaler divides MCLK create the internal clock (PCLK). PCLK is used to clock all portions of the MAX9867. See Table 4. The MAX9867 is capable of supporting any sample rate from 8kHz to 48kHz, including all common sample rates (8kHz, 16kHz, 24kHz, 32kHz, 44 ...
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... PLL mode instead. PLL Mode Enable 0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an LRCLK as specified by the divide ratio. PLL 1 = Valid for slave mode only ...
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... SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867, HIZOFF allowing SDOUT to be shared by other devices SDOUT is set either high or low after all data bits have been transferred out of the MAX9867. Note: High-impedance mode is intended for use when TDM = 1. LVOLFIX See the Line Inputs section ...
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Ultra-Low Power Stereo Audio Codec Table 6. Digital Audio Interface Registers (continued) BITS TDM Mode Select 0 = LRCLK signal polarity indicates left and right audio LRCLK is a framing pulse that transitions polarity to indicate the start ...
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Ultra-Low Power Stereo Audio Codec AUDIO MASTER MODES: LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) D15 D14 D13 D12 D11 D10 ...
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Ultra-Low Power Stereo Audio Codec WCI = 0, BCI = 0, DLY = 1, SDODLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDOUT D15 D14 D13 D12 D11 D10 ...
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Ultra-Low Power Stereo Audio Codec VOICE (TDM, PCM) MASTER MODES: BCI = 0, HIZOFF = 0, SDODLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (SEE NOTE) SDOUT L15 L14 L13 L12 L11 L10 ...
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Ultra-Low Power Stereo Audio Codec AUDIO SLAVE MODES: LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0 LRCLK 25ns (min) D15 D14 D13 D12 D11 D10 ...
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Ultra-Low Power Stereo Audio Codec WCI = 0, BCI = 0, DLY = 1, SDODLY = 0 LRCLK 25ns (min) SDOUT D15 D14 D13 D12 D11 D10 ...
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Ultra-Low Power Stereo Audio Codec VOICE (TDM, PCM) SLAVE MODES: BCI = 0, HIZOFF = 0, SDODLY = 0 LRCLK 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 40ns ...
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... Ultra-Low Power Stereo Audio Codec The MAX9867 incorporates both IIR (voice) and FIR (audio) digital filters to accomodate a wide range of audio sources. The IIR fiilters provide over 70dB of Table 7. Digital Filtering Register REGISTER B7 Codec Filters MODE BITS Digital Audio Filter Mode MODE ...
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... Ultra-Low Power Stereo Audio Codec Digital Gain Control The MAX9867 includes digital gain adjustment for the playback and record paths. Independent gain adjust- ment is provided for the two record channels. Sidetone Table 9. Digital Gain Registers REGISTER B7 Sidetone DSTS DAC Level 0 ADC Level ...
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... ADC Left/Right Level Control SETTING 0x0 0x1 0x2 AVL/AVR 0x3 0x4 0x5 0x6 0x7 The MAX9867 includes one pair of single-ended line inputs. When enabled, the line inputs connect directly Table 10. Line Input Registers REGISTER B7 Left-Line Input Level 0 Right-Line Input Level 0 36 ______________________________________________________________________________________ ...
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... Line input to headphone output volume tracks VOLL and VOLR bits. LVOLFIX 1 = Line input to headphone output volume fixed at VOLL and VOLR bits. See the Digital Audio Interface section. Playback Volume The MAX9867 incorporates volume and mute control to allow level control for the playback audio path. Program Table 11. Playback Volume Registers REGISTER B7 ...
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... Microphone Inputs Two differential microphone inputs and a low-noise micro- phone bias for powering the microphones are provided by the MAX9867. In typical applications, the left micro- phone records a voice signal and the right microphone records a background noise signal. In applications that require only one microphone, use the left microphone input and disable the right ADC ...
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... PGAML/PGAMR 0x04 0x05 0x06 0x07 0x08 0x09 0x0A Figure 5. Microphone Input Signal Path ______________________________________________________________________________________ FUNCTION GAIN (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +10 +11 MAX9867 1.5V MICBIAS 0/20/30dB V REG MICLP PREAMP MICLN - 0/20/30dB V REG MICRP PREAMP MICRN SETTING GAIN (dB) 0x0B +9 0x0C +8 0x0D +7 0x0E ...
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... Wait the appropriate time (see Table 13). 4) Complete calibration (AUXCAL = 0). Perform the following steps the first time a DC measure- Setup Procedure ment is taken after applying power to the MAX9867 or if the temperature changes significantly: 1) Enable the AUX input (AUXEN = 1). 2) Start gain calibration (AUXGAIN = 1). ...
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... Configure the digital audio interface for f (PSCLK = 01, FREQ = 0x0, PLL = 0x5ABE, MAS = 0). 2) Disable JACKSNS (JDETEN = 0). 3) Enable the left and right ADC; take the MAX9867 out of shutdown (ADLEN = ADREN = SHDN = 1). 4) Calibrate the offset: a. Enable the AUX input (AUXEN = 1). ...
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... Ultra-Low Power Stereo Audio Codec Digital Microphone Input The MAX9867 can accept audio from up to two digital microphones. When using digital microphones, the left analog microphone input is retasked as a digital micro- Table 15. Digital Microphone Input Register REGISTER B7 Microphone MICCLK BITS Digital Microphone Clock ...
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... ROUTN OPTIONAL COMPONENTS REQUIRED FOR CLICK AND POP SUPPRESSION ONLY Figure 8. Headphone Amplifier Modes ______________________________________________________________________________________ When the MAX9867 is in normal operation and the micro- phone interface is enabled, jack insertion and removal can be detected through the JACKSNS/AUX pin. As shown in Figure 7, V phone is connected, V ...
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Ultra-Low Power Stereo Audio Codec Table 16. Mode Configuration Register REGISTER B7 Mode DSLEW BITS Digital Volume Slew Speed DSLEW 0 = Digital volume changes are slewed over 10ms Digital volume changes are slewed over 80ms. Volume Change ...
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... ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1. The MAX9867 includes a revision code to allow easy identification of the device revision. The revision code is 0x42. See Table 18 for the revision code register. ...
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... Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condi- tion and a STOP (P) condition. Each word transmitted to the MAX9867 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9867 transmits the proper slave address followed by a series of nine SCL pulses ...
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... The master pulls down SDA during the 9th clock cycle to acknowledge Slave Address receipt of data when the MAX9867 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9867, followed by a STOP condition ...
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... Ultra-Low Power Stereo Audio Codec The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9867. The MAX9867 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master config- ures the MAX9867’ ...
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... SLAVE ADDRESS 0 A REGISTER ADDRESS R/W Figure 15. Reading n Bytes of Data from the MAX9867 Applications Information Proper layout and grounding are essential for optimum performance. When designing a PCB for the MAX9867, partition the circuitry so that the analog sections of the MAX9867 are separated from the digital sections. This ensures that the analog audio traces are not routed near digital traces ...
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... DGND 1 (A2) 1.8V 1.8V 1μF 1μF 1μ (A1) (A4) (A5) DVDD AVDD PREG LINEAR REG DVST: MAX9867 DACA: VOLL: 0dB TO -15dB +6dB TO -84dB DIGITAL DACL FILTERING DACA: VOLR: 0dB TO -15dB +6dB TO -84dB DIGITAL DACR FILTERING VOLL, LVOLFIX: +6dB TO -84dB JACK DETECT VOLR, LVOLFIX: ...
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... BCLK MCLK 14 MICRN B 13 MICRP 12 MICLP/DIGMICDATA LRCLK SDIN C 11 MICLN/DIGMICCLK 10 MICBIAS SDOUT LOUTN 9 AGND D DVDDIO PVDD E Pin Configurations MAX9867 SDA AVDD PREG AGND SCL REF REG MICBIAS IRQ MICRP MICLN MICLP ROUTP JACKSNS LINL MICRN LOUTP ROUTN PGND LINR WLP (2 ...
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Ultra-Low Power Stereo Audio Codec For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 30 WLP 32 TQFN-EP 52 ______________________________________________________________________________________ Package Information PACKAGE CODE W302A2+3 T3255+4 DOCUMENT NO. 21-0211 21-0140 ...
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Ultra-Low Power Stereo Audio Codec For the latest package outline information and land patterns www.maxim-ic.com/packages. ______________________________________________________________________________________ Package Information (continued) 53 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 54 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Package Information (continued) Maxim is a registered trademark of Maxim Integrated Products, Inc. ...