CS42526-CQZ Cirrus Logic Inc, CS42526-CQZ Datasheet - Page 56

• Manufacturer Part Number: CS42526-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42526-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/6 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1037

56
6.9.3
6.9.4
6.10
6.10.1 BURST PREAMBLE BITS (PCX & PDX)
PCx-7
PDx-7
7
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
RECEIVER CLOCK FREQUENCY (RCVR_CLKX)
Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only)
Note:
Default = x
0 - Output of PLL
1 - OMCK
Function:
Default = xxx
Function:
Default = xxh
Function:
This bit identifies the source of the internal system clock (MCLK).
The CS42526 detects the ratio between the OMCK and the recovered clock from the PLL. Given the
absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL
clock.
If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX
bits are set accordingly (see
of the PLL clock is reflected in the RCVR_CLKX bits according to
of the PLL clock does not match one of the frequencies given in
closest available value.
If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents
of the RCVR_CLKX bits will be inaccurate and should be disregarded. In this case, an external con-
troller may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to
determine the absolute frequency of the PLL clock.
The PC and PD burst preamble bytes are loaded into these four registers.
PCx-6
PDx-6
These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
6
RCVR_CLK2 RCVR_CLK1 RCVR_CLK0
0
0
0
0
1
1
1
1
PCx-5
PDx-5
Table 14. Receiver Clock Frequency Detection
5
“OMCK Frequency (OMCK Freqx)” on page
0
0
1
1
0
0
1
1
PCx-4
PDx-4
4
0
1
0
1
0
1
0
1
PCx-3
PDx-3
3
Description
11.2896 MHz
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
8.1920 MHz
12.288 MHz
PCx-2
PDx-2
2
Table
Table
16, these bits will reflect the
16. If the absolute frequency
53), the absolute frequency
PCx-1
PDx-1
1
CS42526
PCx-0
PDx-0
DS585F1
0