L3G4200DHTR STMicroelectronics, L3G4200DHTR Datasheet - Page 22

• Manufacturer Part Number: L3G4200DHTR
• Description: Gyroscopes Digital Gyro 96 FIFO 250 / 500 / 2000 DPS
• Manufacturer: STMicroelectronics

Specifications of L3G4200DHTR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Digital interfaces
4.2.1
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Figure 12. Read and write protocol
CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the
transmission and goes back high at the end. SPC is the serial port clock and is controlled by
the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are,
respectively, the serial port data input and output. These lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses, or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, etc.) starts at the last falling edge of SPC just before
the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip drives SDO at the start of bit 8.
bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto-incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands, further blocks of 8 clock periods are added. When the MS
bit is 0, the address used to read/write data remains the same for every block. When the MS
bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
SPI read
Figure 13. SPI read protocol
SDO
SPC
SDI
CS
SDO
SPC
SDI
CS
RW
MS
RW
AD5 AD4 AD3 AD2 AD1 AD0
MS
AD5 AD4 AD3 AD2 AD1 AD0
Doc ID 17300 Rev 1
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
L3G4200DH