L3G4200DHTR STMicroelectronics, L3G4200DHTR Datasheet - Page 15

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L3G4200DHTR

Manufacturer Part Number
L3G4200DHTR
Description
Gyroscopes Digital Gyro 96 FIFO 250 / 500 / 2000 DPS
Manufacturer
STMicroelectronics
Datasheet

Specifications of L3G4200DHTR

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
L3G4200DH
3
3.1
3.2
3.2.1
Main digital blocks
Block diagram
Figure 6.
FIFO
The L3G4200DH embeds a 32-slot, 16-bit data FIFO for each of the three output channels:
yaw, pitch and roll. This allows consistent power saving for the system, since the host
processor does not need to continuously poll data from the sensor. Instead it can wake up
only when needed and burst the significant data out from the FIFO. This buffer can work in
five different modes. Each mode is selected by the FIFO_MODE bits in the
FIFO_CTRL_REG. Programmable watermark level, FIFO_empty or FIFO_Full events can
be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through
CTRL_REG3, and event detection information is available in FIFO_SRC_REG. Watermark
level can be configured to WTM4:0 in FIFO_CTRL_REG.
Bypass mode
In bypass mode, the FIFO is not operational and for this reason it remains empty. As
illustrated in the
FIFO slots are empty. When new data is available, the old data is overwritten.
Block diagram
Figure
7, only the first address is used for each channel. The remaining
Doc ID 17300 Rev 1
Main digital blocks
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