MPC8313EVRAFFB Freescale Semiconductor, MPC8313EVRAFFB Datasheet - Page 13

IC MPU POWERQUICC II PRO 516PBGA

MPC8313EVRAFFB

Manufacturer Part Number
MPC8313EVRAFFB
Description
IC MPU POWERQUICC II PRO 516PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313EVRAFFB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
333MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8313E-RDB
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
16 KB
I/o Voltage
2.5 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
Program Memory Type
EEPROM/Flash
For Use With
MPC8313E-RDB - BOARD PROCESSOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313EVRAFFB
Manufacturer:
FREESCAL
Quantity:
150
Part Number:
MPC8313EVRAFFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8313E.
5.1
Table 9
5.2
Table 10
Freescale Semiconductor
Input high voltage
Input low voltage
Input current
Output high voltage
Output low voltage
Output low voltage
Required assertion time of HRESET or SRESET (input) to activate reset flow
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
HRESET assertion (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]
and CFG_SYS_CLK_IN_DIV) with respect to negation of PORESET when
the device is in PCI host mode
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]
and CFG_CLKIN_DIV) with respect to negation of PORESET when the
device is in PCI agent mode
Input hold time for POR configuration signals with respect to negation of
HRESET
Time for the device to turn off POR configuration signal drivers with respect
to the assertion of HRESET
RESET Initialization
provides the DC electrical characteristics for the RESET pins.
provides the reset initialization AC timing specifications.
RESET DC Electrical Characteristics
RESET AC Electrical Characteristics
Characteristic
MPC8313E PowerQUICC
Parameter/Condition
Table 10. RESET Initialization Timing Specifications
Table 9. RESET Pins DC Electrical Characteristics
Symbol
V
V
V
V
V
I
OH
IN
OL
OL
IH
IL
II Pro Processor Hardware Specifications, Rev. 3
0 V ≤ V
I
OH
I
I
OL
OL
Condition
= –8.0 mA
= 3.2 mA
= 8.0 mA
IN
≤ NV
DD
Min
512
32
32
32
4
4
0
–0.3
Min
2.1
2.4
Max
4
t
t
t
t
NV
t
t
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
SYS_CLK_IN
SYS_CLK_IN
DD
Max
Unit
0.8
0.5
0.4
±5
ns
ns
RESET Initialization
+ 0.3
Notes
Unit
μA
V
V
V
V
V
1
2
1
1
2
1
3
13

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