MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 41

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3.8 BUS ARBITRATION CONTROL SIGNALS
The following signals are the bus arbitration control signals used to determine which
device in a system is the bus master. Note that BGACK is implemented in the MC68020
and not implemented in the MC68EC020.
Bus Request (BR)
Bus Grant (BG)
Bus Grant Acknowledge (BGACK, MC68020 only)
3.9 BUS EXCEPTION CONTROL SIGNALS
The following signals are the bus exception control signals for the MC68020/EC020.
Reset (RESET)
3-6
This input signal indicates that an external device needs to become the bus master. BR
is typically a “wire-ORed” input (but does not need to be constructed from open-collector
devices). Refer to Section 5 Bus Operation for more information on MC68020 bus
arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an
MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration
Protocol for more information on MC68EC020 bus arbitration.
This output signal indicates that the MC68020/EC020 will release ownership of the bus
when the current processor bus cycle completes. Refer to Section 5 Bus Operation for
more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and
Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-
Wire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration.
This input signal indicates that an external device has become the bus master. Refer to
Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to
Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA
Device That Supports a Three-Wire Bus Arbitration Protocol for more information
on MC68EC020 bus arbitration.
BGACK is not implemented in the MC68EC020.
This bidirectional open-drain signal is used to initiate a system reset. An external reset
signal resets the MC68020/EC020 as well as all external devices. A reset signal from
the processor (asserted as part of the RESET instruction) resets external devices only;
the internal state of the processor is not altered. Refer to Section 5 Bus Operation for
a description of reset bus operation and Section 6 Exception Processing for
information about the reset exception.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
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