MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 200

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

described in Section 6 Exception Processing. The vector number for the exception is
taken from the vector number field of the primitive, and the MC68020/EC020 uses the
four-word stack frame format shown in Figure 7-41.
The value of the PC saved in this stack frame is the F-line operation word address of the
coprocessor instruction during which the primitive was received. Thus, if the exception
handler routine does not modify the stack frame, an RTE instruction causes the
MC68020/EC020 to return and reinitiate execution of the coprocessor instruction.
The take preinstruction exception primitive can be used when the coprocessor does not
recognize a value written to either its command CIR or condition CIR to initiate a
coprocessor instruction. This primitive can also be used if an exception occurs in the
coprocessor instruction before any program-visible resources are modified by the
instruction operation. This primitive should not be used during a coprocessor instruction if
program-visible resources have been modified by that instruction. Otherwise, since the
MC68020/EC020 reinitiates the instruction when it returns from exception processing, the
restarted instruction receives the previously modified resources in an inconsistent state.
One of the most important uses of the take preinstruction exception primitive is to signal
an exception condition in a cpGEN instruction that was executing concurrently with the
main processor's instruction execution. If the coprocessor no longer requires the services
of the main processor to complete a cpGEN instruction and if the concurrent instruction
completion is transparent to the programming model, the coprocessor can release the
main processor by issuing a primitive with CA = 0. The main processor usually executes
the next instruction in the instruction stream, and the coprocessor completes its operations
concurrently with the main processor operation. If an exception occurs while the
coprocessor is executing an instruction concurrently, the exception is not processed until
the main processor attempts to initiate the next general or conditional instruction. After the
main processor writes to the command or condition CIR to initiate a general or conditional
instruction, it then reads the response CIR. At this time, the coprocessor can return the
take preinstruction exception primitive. This protocol allows the main processor to proceed
with exception processing related to the previous concurrently executing coprocessor
instruction and then return and reinitiate the coprocessor instruction during which the
exception was signaled. The coprocessor should record the addresses of all general
category instructions that can be executed concurrently with the main processor and that
support exception recovery. Since the exception is not reported until the next coprocessor
instruction is initiated, the processor usually requires the instruction address to determine
MOTOROLA
Figure 7-41. MC68020/EC020 Preinstruction Stack Frame
SP
+02
+06
Freescale Semiconductor, Inc.
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For More Information On This Product,
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Go to: www.freescale.com
M68020 USER’S MANUAL
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PROGRAM COUNTER
STATUS REGISTER
VECTOR NUMBER
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