MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 23

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The SR (see Figure 1-4) stores the processor status. It contains the condition codes that
reflect the results of a previous operation and can be used for conditional instruction
execution in a program. The condition codes are extend (X), negative (N), zero (Z),
overflow (V), and carry (C). The user byte, which contains the condition codes, is the only
portion of the SR information available in the user privilege level, and it is referenced as
the CCR in user programs. In the supervisor privilege level, software can access the entire
SR, including the interrupt priority mask (three bits) and control bits that indicate whether
the processor is in:
The VBR contains the base address of the exception vector table in memory. The
displacement of an exception vector is added to the value in this register to access the
vector table.
The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the
MC68020, function codes can be considered extensions of the 32-bit linear address that
optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020,
function codes can be considered extensions of the 24-bit linear address that optionally
provide as many as eight 16-Mbyte address spaces. Function codes are automatically
generated by the processor to select address spaces for data and program at the user
and supervisor privilege levels and to select a CPU address space for processor functions
(e.g., coprocessor communications). Registers SFC and DFC are used by certain
instructions to explicitly specify the function codes for operations.
The CACR controls the on-chip instruction cache of the MC68020/EC020. The CAAR
stores an address for cache control functions.
MOTOROLA
1. One of two trace modes (T1, T0)
2. Supervisor or user privilege level (S)
3. Master or interrupt mode (M)
MASTER/INTERRUPT MODE
SUPERVISOR/USER LEVEL
T1
ENABLE
15
TRACE
Freescale Semiconductor, Inc.
T0
14
For More Information On This Product,
Figure 1-4. Status Register (SR)
13
S
SYSTEM BYTE
12
M
Go to: www.freescale.com
M68020 USER’S MANUAL
11
0
PRIORITY MASK
10
I2
INTERRUPT
I1
9
I0
8
7
0
(CONDITION CODE REGISTER)
6
0
5
0
USER BYTE
4
X
N
3
2
Z
1
V
0
C
CARRY
OVERFLOW
ZERO
NEGATIVE
EXTEND
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