MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 283

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

AC ELECTRICAL CHARACTERISTICSÑREAD AND WRITE CYCLES
*
**
MOTOROLA
This specification does not apply to the MC68EC020.
*
Num.
*
These specifications represent an improvement over previously published specifications for the 25-MHz MC68020
31A
*
59
29A
37A
39A
47A
47B
(Continued)
31
*
*
*
*
*
*
48
58
and are valid only for product bearing date codes of 8827 and later.
29
30
32
33
34
35
39
45
46
53
55
56
57
37
40
41
42
43
44
10
2
4
10
5
3
6
AS, DS Negated to Data-In Invalid
AS, DS Negated to Data-In
Clock Low to Data-In Invalid
DSACK» Asserted to Data-In Valid
DSACK» Asserted to DSACK» Valid
RESET Input Transition Time
Clock Low to BG Asserted
Clock Low to BG Negated
BR Asserted to BG Asserted (RMC Not
BGACK Asserted to BG Negated
BGACK Asserted to BR Negated
BG Width Negated
BG Width Asserted
Clock High to DBEN Asserted (Read)
Clock Low to DBEN Negated (Read)
Clock Low to DBEN Asserted (Write)
Clock High to DBEN Negated (Write)
R/W Low to DBEN Asserted (Write)
DBEN Width Asserted
R/W Width Valid (Write or Read)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK» Asserted to BERR, HALT Asserted
Data-Out Hold from Clock High
R/W Valid to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
BGACK Negated to Bus Driven
BG Negated to Bus Driven
(Data-In Hold Time)
(High Impedance)
(Data-In Hold Time)
(DSACK» Asserted Skew)
Asserted)
Characteristics
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68020 USERÕS MANUAL
Read
Write
16.67 MHz
Min
120
150
512
1.5
1.5
15
90
90
15
60
15
30
Ñ
Ñ
Ñ
Ñ
Ñ
0
0
0
0
0
0
0
0
5
0
0
1
1
Max
1.5
3.5
3.5
1.5
60
50
15
30
30
30
30
30
30
30
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Min
100
125
512
1.5
1.5
15
75
75
10
50
15
25
Ñ
Ñ
Ñ
Ñ
Ñ
0
0
0
0
0
0
0
0
5
0
0
1
1
20 MHz
Max
1.5
3.5
3.5
1.5
50
43
10
25
25
25
25
25
25
20
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Min
100
512
1.5
1.5
10
60
60
10
40
80
10
20
25 MHz
Ñ
Ñ
Ñ
Ñ
Ñ
0
0
0
0
0
0
0
0
5
0
0
1
1
Max
1.5
3.5
3.5
1.5
40
32
10
20
20
20
20
20
20
18
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
**
33.33 MHz
Min
512
1.5
1.5
10
50
50
30
60
75
10
20
Ñ
Ñ
Ñ
Ñ
Ñ
0
0
0
0
0
0
0
0
5
5
0
0
1
1
Max
1.5
3.5
3.5
1.5
30
17
10
20
20
15
15
15
15
15
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Unit
Clks
Clks
Clks
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10-9