MC68HC000EI8 Freescale Semiconductor, MC68HC000EI8 Datasheet - Page 99
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MC68HC000EI8
Manufacturer Part Number
MC68HC000EI8
Description
IC MPU 16BIT 8MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68HC000EI8
Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
8MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC000EI8
Manufacturer:
FREESCALE
Quantity:
3 400
Company:
Part Number:
MC68HC000EI8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68HC000EI8R2
Manufacturer:
FREESCAL
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Company:
Part Number:
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Manufacturer:
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Quantity:
10 000
A signed divide (DIVS) or unsigned divide (DIVU) instruction forces an exception if a
division operation is attempted with a divisor of zero.
6.3.6 Illegal and Unimplemented Instructions
Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal M68000 instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define
instructions using the opcodes of any of the illegal instructions. Three bit patterns always
force an illegal instruction trap on all M68000-Family-compatible microprocessors. The
patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are
reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer
use (as the take illegal instruction trap (ILLEGAL) instruction).
Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit
efficient emulation. Opcodes beginning with bit patterns equaling 1111 (line F) are
implemented in the MC68020 and beyond as coprocessor instructions. These separate
vectors allow the operating system to emulate unimplemented instructions in software.
Exception processing for illegal instructions is similar to that for traps. After the instruction
is fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
for group 2 is then pushed on the supervisor stack, and the illegal instruction vector is
fetched.
6-14
In addition to the previously defined illegal instruction opcodes,
the MC68010 defines eight breakpoint (BKPT) instructions with
the bit patterns $4848–$484F. These instructions cause the
processor to enter illegal instruction exception processing as
usual. However, a breakpoint acknowledge bus cycle, in which
the function code lines (FC2–FC0) are high and the address
lines are all low, is also executed before the stacking
operations are performed. The processor does not accept or
send any data during this cycle. Whether the breakpoint
acknowledge cycle is terminated with a DTACK, BERR, or VPA
signal, the processor continues with the illegal instruction
processing. The purpose of this cycle is to provide a software
breakpoint that signals to external hardware when it is
executed.
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MOTOROLA