MC68HC000EI8 Freescale Semiconductor, MC68HC000EI8 Datasheet - Page 53

• Manufacturer Part Number: MC68HC000EI8
• Description: IC MPU 16BIT 8MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 8MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

STATE 7
5.1.3 Read-Modify-Write Cycle.
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe ( AS) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between
processors in a multiprocessing environment. The TAS instruction (the only instruction
that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write
cycles are byte operations. The read-modify-write flowchart shown in Figure 5-8 and the
timing diagram in Figure 5-9, applies to the MC68000, the MC68HC000, the MC68HC001
(in 16-bit mode), the MC68EC000 (in 16-bit mode), and the MC68010.
MOTOROLA
1) SET R/W TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A23–A1
4) ASSERT ADDRESS STROBE (AS)
5) ASSERT UPPER DATA STROBE (UDS)
1) LATCH DATA
1) NEGATE UDS AND LDS
2) START DATA MODIFICATION
1) SET R/W TO WRITE
2) PLACE DATA ON D7–D0 OR D15–D8
3) ASSERT UPPER DATA STROBE (UDS)
1) NEGATE UDS OR LDS
2) NEGATE AS
3) REMOVE DATA FROM D7–D0 OR
4) SET R/W TO READ
OR LOWER DATA STROBE (LDS)
OR LOWER DATA STROBE (LDS)
D15–D8
TERMINATE OUTPUT TRANSFER
START OUTPUT TRANSFER
ADDRESS THE DEVICE
On the falling edge of the clock entering S7, the processor negates AS,
UDS, or LDS. As the clock rises at the end of S7, the processor places
the address and data buses in the high-impedance state, and drives R/W
high. The device negates DTACK or BERR at this time.
ACQUIRE THE DATA
START NEXT CYCLE
BUS MASTER
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Figure 5-8. Read-Modify-Write Cycle Flowchart
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
1) DECODE ADDRESS
2) PLACE DATA ON D7–D0 OR D15–D0
3) ASSERT DATA TRANSFER
1) REMOVE DATA FROM D7–D0
2) NEGATE DTACK
1) STORE DATA ON D7–D0 OR D15–D8
2) ASSERT DATA TRANSFER
1) NEGATE DTACK
ACKNOWLEDGE (DTACK)
OR D15–D8
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
TERMINATE THE CYCLE
INPUT THE DATA
INPUT THE DATA
SLAVE
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