MC68HC000EI8 Freescale Semiconductor, MC68HC000EI8 Datasheet - Page 60
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MC68HC000EI8
Manufacturer Part Number
MC68HC000EI8
Description
IC MPU 16BIT 8MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68HC000EI8
Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
8MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC000EI8
Manufacturer:
FREESCALE
Quantity:
3 400
Company:
Part Number:
MC68HC000EI8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68HC000EI8R2
Manufacturer:
FREESCAL
Quantity:
8 831
Company:
Part Number:
MC68HC000EI8R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
The timing diagram in Figure 5-15 shows that the bus request is negated at the time that
an acknowledge is asserted. This type of operation applies to a system consisting of a
processor and one other device capable of becoming bus master. In systems having
several devices that can be bus masters, bus request lines from these devices can be
wire-ORed at the processor, and more than one bus request signal could occur.
The bus grant signal is negated a few clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus requests are pending, the processor reasserts bus
grant for another request a few clock cycles after bus grant (for the previous request) is
negated. In response to this additional assertion of bus grant, external arbitration circuitry
selects the next bus master before the current bus master has completed the bus activity.
The timing diagram in Figure 5-15 also applies to a system consisting of a processor and
one other device capable of becoming bus master. Since the 48-pin version of the
MC68008 and the MC68EC000 does not recognize a bus grant acknowledge signal, this
processor does not negate bus grant until the current bus master has completed the bus
activity.
5.2.1 Requesting The Bus
External devices capable of becoming bus masters assert BR to request the bus. This
signal can be wire-ORed (not necessarily constructed from open-collector devices) from
any of the devices in the system that can become bus master. The processor, which is at
a lower bus priority level than the external devices, relinquishes the bus after it completes
the current bus cycle.
The bus grant acknowledge signal on all the processors except the 48-pin MC68008 and
MC68EC000 helps to prevent the bus arbitration circuitry from responding to noise on the
5-14
FC2–FC0
A19–A0
DTACK
D7–D0
CLK
R/W
DS
BR
BG
AS
PROCESSOR
S0
S2 S4
Figure 5-16. 2-Wire Bus Arbitration Timing Diagram
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
S6
Freescale Semiconductor, Inc.
DMA DEVICE
For More Information On This Product,
S0 S2 S4 S6
Go to: www.freescale.com
S0 S2 S4 S6 S0 S2 S4 S6
PROCESSOR
DMA DEVICE
MOTOROLA