MC68HC000EI8 Freescale Semiconductor, MC68HC000EI8 Datasheet - Page 70
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MC68HC000EI8
Manufacturer Part Number
MC68HC000EI8
Description
IC MPU 16BIT 8MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68HC000EI8
Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
8MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC000EI8
Manufacturer:
FREESCALE
Quantity:
3 400
Company:
Part Number:
MC68HC000EI8
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68HC000EI8R2
Manufacturer:
FREESCAL
Quantity:
8 831
Company:
Part Number:
MC68HC000EI8R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
The MC68010 also differs from the other microprocessors described in this manual
regarding bus errors. The MC68010 can detect a late bus error signal asserted within one
clock cycle after the assertion of data transfer acknowledge. When receiving a bus error
signal, the processor can either initiate a bus error exception sequence or try running the
cycle again.
5.4.1 Bus Error Operation
In all the microprocessors described in this manual, a bus error is recognized when
DTACK and HALT are negated and BERR is asserted. In the MC68010, a late bus error is
also recognized when HALT is negated, and DTACK and BERR are asserted within one
clock cycle.
When the bus error condition is recognized, the current bus cycle is terminated in S9 for a
read cycle, a write cycle, or the read portion of a read-modify-write cycle. For the write
portion of a read-modify-write cycle, the current bus cycle is terminated in S21. As long as
BERR remains asserted, the data and address buses are in the high-impedance state.
Figure 5-25 shows the timing for the normal bus error, and Figure 5-26 shows the timing
for the MC68010 late bus error.
5-24
FC2–FC0
LDS/UDS
D15–D0
A23–A1
DTACK
BERR
HALT
R/W
CLK
AS
S0
INITIATE
READ
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
S2
Figure 5-25. Bus Error Timing Diagram
Freescale Semiconductor, Inc.
S4
For More Information On This Product,
RESPONSE
FAILURE
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Go to: www.freescale.com
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S6
BUS ERROR
DETECTION
S8
ERROR STACKING
INITIATE BUS
MOTOROLA