FWIXP420BB Intel, FWIXP420BB Datasheet - Page 40
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FWIXP420BB
Manufacturer Part Number
FWIXP420BB
Description
IC NETWRK PROCESSR 266MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BB
Processor Type
Network
Features
XScale Core
Speed
266MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
852278
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BB
Manufacturer:
MICRON
Quantity:
2 198
Part Number:
FWIXP420BB
Manufacturer:
INTEL
Quantity:
20 000
Intel
Functional Signal Descriptions
Table 14.
Table 15.
Table 16.
40
®
IXP42X Product Line and IXC1100 Control Plane Processor
Oscillator Interface
GPIO Interface
JTAG Interface
OSC_IN
OSC_OUT
†
GPIO[12:0]
GPIO[13]
GPIO[14]
GPIO[15]
†
†
JTG_TRST_N
Name
JTG_TMS
JTG_TDO
JTG_TCK
For a legend of the Type codes, see
For a legend of the Type codes, see
For a legend of the Type codes, see
Name
JTG_TDI
Name
Power
Reset
Reset
Power
On
Z
Z
Z
Z
On
Reset
Power
†
On
†
H
H
H
Z
Z
CLKOUT
Reset
†
Reset
/VO
Z
Z
Z
Reset
VI/PE
VI/PE
VI/PE
†
†
VO
VI
Table 4 on page
Table 4 on page
Table 4 on page
Type
Type
†
O
I/O
I/O
I/O
I/O
I
†
Type
†
O
I
I
I
I
33.33-MHz, sinusoidal crystal input signal. Can be driven by an oscillator.
33.33-MHz, sinusoidal crystal output signal. Left disconnected when being
driven by an oscillator.
General purpose Input/Output pins. May be configured as an input or an
output. As an input, each signal may be configured a processor interrupt.
Default after reset is to be configured as inputs.
Should be pulled low using a 10-KΩ resistor when not being utilized in the
system.
General purpose input/output pins. May be configured as an input or an
output. Default after reset is to be configured as inputs.
Should be pulled low using a 10-KΩ resistor when not being utilized in the
system.
Can be configured similar to GPIO Pin 13 or as a clock output. Configuration
as an output clock can be set at various speeds of up to 33.33 MHz with
various duty cycles. Configured as an input, upon reset.
Should be pulled low though a 10-KΩ resistor when not being utilized in the
system.
Can be configured similar to GPIO Pin 13 or as a clock output. Configuration
as an output clock can be set at various speeds of up to 33.33 MHz with
various duty cycles. Configured as an output, upon reset. Can be used to
clock the expansion interface, after reset.
Should be pulled low though a 10-KΩ resistor when not being utilized in the
system.
†
30.
30.
30.
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
The JTG_TRST_N signal must be asserted (driven low) during
power-up, otherwise the TAP controller may not be initialized properly,
and the processor may be locked.
When the JTAG interface is not being used, the signal must be pulled low
using a 10-KΩ resistor.
Used as the clock for the IEEE 1149.1 JTAG interface.
Description
Description
Description
Datasheet