FWIXP420BB Intel, FWIXP420BB Datasheet - Page 31

• Manufacturer Part Number: FWIXP420BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of FWIXP420BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 266MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 852278

Datasheet
Table 5.
Note:
This section’s other tables include:
SDRAM Interface (Sheet 1 of 2)
1. The Power On Reset Column of the Tables indicate the state of the signals during the Power On Reset
2. The Reset Column of the Tables indicate the state of the signals during the Reset.
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CLKOUT
SDM_BA[1:0]
SDM_RAS_N
SDM_CAS_N
SDM_CS_N[1:0]
SDM_WE_N
† For a legend of the
•
•
•
•
•
•
•
•
•
•
•
•
•
•
process
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRAM Interface
PCI Controller
High-Speed, Serial Interface 0
High-Speed, Serial Interface 1
MII Interfaces
UTOPIA-2 Interface
Expansion Bus Interface
UART Interfaces
USB Interface
Oscillator Interface
GPIO Interface
JTAG Interface
System Interface
Power Interface
Reset
Power
on
Type
Z
Z
Z
Z
Z
Z
Z
Z
Intel
†
codes, see
Reset
®
0
1
0
0
1
1
1
1
IXP42X Product Line and IXC1100 Control Plane Processor
signals
signals
†
signals
signals
signals
signals
Table 4 on page
Type
signals
signals
signals
I/O
O
O
O
O
O
O
O
signals
signals
†
SDRAM Address: A0-A12 signals are output during the READ/WRITE
commands and ACTIVE commands to select a location in memory to act
upon.
SDRAM Data: Bidirectional data bus used to transfer data to and from the
SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the rising edge
of SDM_CLKOUT. All output signals are driven with respect to the rising
edge of SDM_CLKOUT.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the
current command is attempting to access.
SDRAM Row Address strobe/select (active low): Along with
SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals determines the
current command to be executed.
SDRAM Column Address strobe/select (active low): Along with
SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals determines the
current command to be executed.
SDRAM Chip select (active low): CS# enables the command decoder in
the external SDRAM when logic low and disables the command decoder
in the external SDRAM when logic high.
SDRAM Write enable (active low): Along with SDM_CAS_N,
SDM_RAS_N, and SDM_CS_N signals determines the current command
to be executed.
signals
signals
signals
30.
Functional Signal Descriptions
Description
31