FWIXP420BB Intel, FWIXP420BB Datasheet - Page 21
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
FWIXP420BB
Manufacturer Part Number
FWIXP420BB
Description
IC NETWRK PROCESSR 266MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BB
Processor Type
Network
Features
XScale Core
Speed
266MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
852278
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BB
Manufacturer:
MICRON
Quantity:
2 198
Part Number:
FWIXP420BB
Manufacturer:
INTEL
Quantity:
20 000
Datasheet
2.1.8
2.1.9
The memory controller internally interfaces to the North AHB and South AHB with independent
interfaces. This architecture allows SDRAM transfers to be interleaved and pipelined to achieve
maximum possible efficiency.
The maximum burst size supported to the SDRAM interface is eight 32-bit words. This burst size
allows the best efficiency/fairness performance between accesses from the North AHB and the
South AHB.
Expansion Bus
The expansion interface allows easy and — in most cases — glue-less connection to peripheral
devices. It also provides input information for device configuration after reset. Some of the
peripheral device types are flash, ATM control interfaces, and DSPs used for voice applications.
(Some voice configurations can be supported by the HSS interfaces and the Intel XScale
implementing voice-compression algorithms.)
The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to
16 Mbytes, using 24 address lines for each of the eight independent chip selects.
Accesses to the expansion bus interface consists of five phases. Each of the five phases can be
lengthened or shortened by setting various configuration registers on a per-chip-select basis. This
feature allows the IXP42X product line and IXC1100 control plane processors to connect to a wide
variety of peripheral devices with varying speeds.
The expansion bus interface supports Intel or Motorola* microprocessor-style bus cycles. The bus
cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for
each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments HPI-8 or
HPI-16 style accesses for DSPs.
The expansion bus interface is an asynchronous interface to externally connected chips. However,
a clock must be supplied to the IXP42X product line and IXC1100 control plane processors’
expansion bus interface for the interface to operate. This clock can be driven from GPIO 15 or an
external source. The maximum clock rate that the expansion bus interface can accept is
66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration information
from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are
used to tie the signals to particular logic levels. (For additional details, see
Information” on page
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer speeds from
512 KHz to 8.192 MHz, for some models of the IXP42X product line and IXC1100 control plane
processors. (See
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the
IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are
capable of supporting various protocols, based on the implementation of the code developed for the
network processor engine core. For a list of supported protocols, see the Intel
Programmer’s Guide.
Table 3 on page
Intel
42.)
®
IXP42X Product Line and IXC1100 Control Plane Processor
17.)
Functional Overview
“Package and Pinout
®
IXP400 Software
®
Core,
21