FWIXP420BB Intel, FWIXP420BB Datasheet - Page 101
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FWIXP420BB
Manufacturer Part Number
FWIXP420BB
Description
IC NETWRK PROCESSR 266MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BB
Processor Type
Network
Features
XScale Core
Speed
266MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
266MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
852278
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BB
Manufacturer:
MICRON
Quantity:
2 198
Part Number:
FWIXP420BB
Manufacturer:
INTEL
Quantity:
20 000
Datasheet
Table 59.
Figure 30.
HPI-16 Multiplexed Write Accesses Values
NOTES:
HPI-16 Multiplex Write Mode
1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for
2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks
3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks
4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3
6. One cycle is the period of the Expansion Bus clock.
7. Timing tests were performed with a 70-pF capacitor to ground.
EX_ADDR[2:1]
T
T
T
T
T
the address phase. This setting is required to ensure that in the event of an HRDY, the Intel
Line and Intel
the address phase for at least one clock pulse after the HRDY is de-active.
for setup phase.
for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
Line and Intel
the data setup phase for at least one clock pulse after the HRDY is de-active
Expansion Bus interface.
until HRDY is de-active
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
EX_RDY_N
data_hold
T
EX_W R_N
EX_RD_N
EX_DATA
EX_CS_N
recov
(hds1_n)
(hr_w_n)
EX_CLK
(hcs_n)
(hcntl)
(hrdy)
(hdin)
Tcs2hds1val
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
Time required between successive accesses on the
expansion interface.
®
®
IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold
T1
Intel
Tdata_setup
Thds1_pulse
T2
®
IXP42X Product Line and IXC1100 Control Plane Processor
Parameter
Tadd_setup
T3
Valid
Data
Tdata_hold
T4
Trecov
T5
T1 T2
Electrical Specifications
Min.
11
3
4
4
4
2
Max
45
36
17
4
5
5
.
Valid
T3
®
®
Cycles 2, 4, 5
Cycles 3, 5, 6
Cycles 3, 6
Cycles 1, 5, 6
Cycles 5, 6
Cycles 4, 6
Data
Units
IXP4XX Product
IXP4XX Product
Notes
T4
101