GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 22

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Intel
2.6
2.6.1
22
Table 10. PCI Configuration Options
®
IXP1240 Network Processor
PCI Unit
The PCI Unit provides an industry standard 32-bit PCI Bus to interface to PCI peripheral devices
such as host processors and MAC devices. The PCI Unit supports operating speeds from DC up to
66 MHz, and supports PCI Local Bus Specification, Revision 2.2. This unit contains:
Refer to the IXP1200 Network Processor Family Hardware Reference Manual for details on PCI
Bus behavior for Target (Slave) and Initiator (Master) modes, configuration and register
definitions.
The PCI interface is specified to operate from DC up to 66 MHz. Above 33 MHz operation, two
PCI devices are supported only, the IXP1240 and a second PCI device. To increase the number of
PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI
bridge device, such the Intel 21150, 21152, or 21153 is required.
Both PCI Initiator and Target cycles are supported. As a target device, the IXP1240 responds as a
Medium Speed device asserting DEVSEL_L two PCI_CLK cycles after FRAME_L is asserted.
PCI Arbitration and Central Function Support
The IXP1240 contains an optional arbiter to support up to three PCI Bus masters. This includes the
IXP1240 plus two external PCI Bus master devices. The external masters are supported by two
request signals, REQ_L[1:0], and two grant signals GNT_L[1:0].
The IXP1240 can also provide PCI Central Function support. In this configuration, the IXP1240:
Two configuration pins, PCI_CFN[1:0], are sampled at the rising edge of RESET_IN_L to
determine the PCI configuration (see
00
10
01
11
•
•
•
•
•
•
•
PCI_CFN[1:0]
Arbitration logic to support up to three PCI Bus masters,
PCI Intelligent I/O (I
Two DMA channels, and
Four 24-bit timers.
Drives the PCI Reset signal, PCI_RST_L, as an output,
Monitors the PCI System Error input signal, SERR_L, and
Provides Bus Parking where the IXP1240 is the default PCI Bus master, and it drives valid
logic levels on the PCI A/D, C/BE, and PAR pins during reset and idle PCI Bus conditions.
Central Function and Arbitration disabled.
Reserved for future use.
Reserved for future use.
Central Function and Arbitration enabled.
2
O),
PCI FUNCTION
Table
10).
Datasheet