GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 16

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

Intel
2.5.2
16
Figure 3. SDRAM Unit Block Diagram
®
IXP1240 Network Processor
Figure 3
The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS_L, CAS_L, write
enable, DQM control, and a synchronous output clock running at one-half the IXP1240 core
frequency (0.5*F
The PCI, Microengines, and StrongARM* core require single byte, word, and longword write
capabilities. The SDRAM Unit supports this using a read-modify-write technique. As data is
written from the PCI or StrongARM* core to SDRAM, a quadword is read from SDRAM. The
IXP1240 then updates only the bytes that were enabled and writes the entire quadword of data back
to SDRAM memory. (Note that the bytes do not have to be consecutive.) These three steps are
performed automatically.
SDRAM Bus Access Behavior
•
•
•
The number of quadwords transferred by the SDRAM Unit is determined by the requesting
interface (StrongARM* core, Microengine, or PCI). The SDRAM Unit may reorder SDRAM
accesses for best performance.
Accesses are always quadword (64-bit) cycles on the SDRAM Bus.
Accesses from the StrongARM* core.
* Other names and brands may be claimed as the property of others.
** ARM architecture compatible
— Byte, word, and longword accesses generated from the StrongARM* core result in
— Consecutive longword writes over the AMBA Bus to the same quadword address are
SDRAM
256 MB
up to
details the major components of the SDRAM Unit.
Read-Modify-Write cycles to SDRAM space.
buffered and aggregated into quadword writes to SDRAM.
WE_L,RAS_L
CAS_L, DQM
Data[63:0]
Addr[14:0]
core
SDCLK
).
Interface
SDRAM
Pin
data
addr
& Address
Command
Generator
Decoder
Microengine Data [63:0]
Machine & Registers
Service Priority
(Arbitration)
AMBA Data
Memory/
FIFO
Microengine Address
& Command Queues
AMBA Address
(High Priority, Even,
RD/Wr Queue
Rd/Wr Queue
PCI Address
Odd & Order)
AMBA Bus
Interface
Logic
(from
StrongARM *
Core)
AMBA[31:0]
PCI Commands
and Addresses
Microengine
Commands &
Addresses
Datasheet
A8907-01