GCIXP1240AC Intel, GCIXP1240AC Datasheet - Page 21

• Manufacturer Part Number: GCIXP1240AC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1240AC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837152

2.5.5.4
Datasheet
Table 9. BootROM x16 Sample Configurations
SRAM Bus Access Behavior
•
•
•
•
•
512 Kbytes - 4 Mbytes
1 Mbytes - 4 Mbytes
2Mbytes - 4 Mbytes
The SRAM controller within the IXP1240 will never initiate automatic bursting. Bursting is
controlled by the requestor (StrongARM* core or Microengine) depending on the type and
number of SRAM accesses needed.
Accesses are always longword 32-bit cycles on the SRAM Bus.
The IXP1240 always drives the address for each data cycle. No external address generation or
address advance control to SRAM devices is required.
Accesses from the StrongARM* core:
Accesses from the Microengines:
— Byte, word, and longword accesses generated from the StrongARM* core are supported.
— Bit operations are supported via StrongARM* core accesses to the SRAM Alias Address
— Bit, byte, and word writes result in Read-Modify-Write cycles.
— Declare memory-mapped I/O as non-cachable to prevent line fill burst cycles, and disable
— For best performance, use longword accesses to avoid Read-Modify-Write cycles on the
— The sram microinstruction defines the number of 32-bit accesses to make, up to 8
— Only bit and longword accesses are supported.
— Bit write accesses result in Read-Modify-Write cycles.
— Unlike the StrongARM* core, the Microengine microinstruction allows you to perform
Total Memory
256 Kbytes
512 Kbytes
1 Mbytes
Space to perform the same operations as a Microengine can accomplish implicitly in a
microinstruction (Push, Pop, Bit Test and Set, CAM operations, Lock/Unlock, etc.).
caching and write buffering to ensure I/O device coherency.
SRAM Bus that occur with byte and word accesses.
longwords with one Microengine command.
bit operations within the instruction (Push, Pop, Bit Test and Set, CAM operations,
Lock/Unlock, etc.).
Number of Chips
(Maximum of 8)
2 - 8
2 - 8
2 - 4
1
1
1
Size of Boot ROM
Intel
2 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
8 Mbit
®
IXP1240 Network Processor
Device Organization
128 K x 16-bit
128 K x 16-bit
256 K x 16-bit
256 K x 16-bit
512 K x 16-bit
512 K x 16-bit
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