TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 41

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 12-2.
12.4
12.4.1
12.4.2
5410B–HIREL–09/05
Exception Type
Instruction
address
breakpoint
System
management
interrupt
Reserved
Memory Management
PowerPC Memory Management
PowerPC 603R Microprocessor Memory Management
Exceptions and Conditions (Continued)
01500–02FFF
Vector Offset
01300
01400
(hex)
The following subsections describe the memory management features of the PowerPC architec-
ture, and the 603R implementation, respectively.
The primary functions of the MMU are to translate logical (effective) addresses to physical
addresses for memory accesses, and to provide access protection on blocks and pages of
memory.
There are two types of accesses generated by the 603R that require address translation —
instruction accesses, and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual mem-
ory management permits execution of programs larger than the size of physical memory;
demand-paged implies that individual pages are loaded into physical memory from system
memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between vir-
tual page numbers and physical page numbers. The page table size is a power of 2, and its
starting address is a multiple of its size.
The page table contains a number of Page Table Entry Groups (PTEGs). A PTEG contains eight
Page Table Entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long. PTEG
addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
The instruction and data memory management units in the 603R provide 4 Gbytes of logical
address space accessible to the supervisor and user programs with a 4 Kbyte page size and
256M byte segment size. Block sizes range from 128 Kbytes to 256 Mbytes and are software
selectable. In addition, the 603R uses an interim 52-bit virtual address and hashed page tables
for generating 32-bit physical addresses. The MMUs in the 603R rely on the exception process-
ing mechanism for the implementation of the paged virtual memory environment and for
enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access,
incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the most
recently used page table entries. The software is responsible for maintaining the consistency of
the TLB with memory.
Causing Conditions
An instruction address breakpoint exception occurs when the address (bits 0-29) in the
IABR matches the next instruction to complete in the completion unit, and the IABR enable
bit (bit 30) is set to 1
A system management interrupt is caused when MSR[EE] = 1 and the SMI input signal is
asserted
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TSPC603R
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