TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 29

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
5410B–HIREL–09/05
General-purpose Registers (GPRs)
Floating-point Registers (FPRs)
Condition Register (CR)
Floating-Point Status and Control Register (FPSCR)
Machine State Register (MSR)
Segment Registers (SRs)
Having access to privilege instructions, registers, and other resources allows the operating sys-
tem to control the application environment (providing virtual memory and protecting operating
system and critical machine resources). Instructions that control the state of the processor, the
address translation mechanism, and supervisor registers can be executed only when the pro-
cessor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603R.
The PowerPC architecture defines 32 user-level, General-purpose Registers (GPRs). These
registers are either 32 bits wide in 32-bit PowerPC microprocessors or 64 bits wide in 64-bit
PowerPC microprocessors. The GPRs serve as the data source or destination for all integer
instructions.
The PowerPC architecture also defines 32 user-level, 64-bit Floating-point Registers (FPRs).
The FPRs serve as the data source or destination for floating-point instructions. These registers
can contain data objects of either single- or double-precision floating-point formats.
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of
certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
The Floating-point Status and Control Register (FPSCR) is a user-level register that contains all
exception signal bits, exception summary bits, exception enable bits, and rounding control bits
needed for compliance with the IEEE 754 standard.
The Machine State Register (MSR) is a supervisor-level register that defines the state of the pro-
cessor. The contents of this register are saved when an exception is taken and restored when
the exception handling is completed. The 603R implements the MSR as a 32-bit register, 64-bit
PowerPC processors implement a 64-bit MSR.
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit Segment
Registers (SRs). To speed access, the 603R implements the segment registers as two arrays; a
main array (for data memory accesses) and a shadow array (for instruction memory accesses).
Loading a segment entry with the Move to Segment Register (STSR) instruction loads both
arrays.
TSPC603R
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