PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 34

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

PLL Configuration
Table 19. PC8240 Microprocessor PLL Configuration
Notes:
34
Ref
1A
1C
1D
1E
1F
10
12
14
16
18
A
C
E
0
1
2
3
4
5
7
8
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0 – 4] settings must be chosen such that the resulting peripheral
2. The processor HID1 values only represent the multiplier of the processor’s PLL (Memory to Processor Multiplier), thus mul-
3. PLL_CFG[0 – 4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011)
4. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is dis-
PC8240
PLL_ CFG
logic/ memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum
or minimum operating frequencies shown in Table. Bold font numerical pairs indicate input range limit and limiting
parameter.
tiple PC8240 PLL_CFG[0 – 4] values may have the same processor HID1 value. This implies that system software cannot
read the HID1 register and associate it with a unique PLL_CFG[0 – 4] value.
are reserved.
abled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for factory use only. The AC timing
specifications given in this document do not apply in PLL Bypass mode.
[0 – 4]
00000
00001
00010
00011
00100
00101
00111
01000
01010
01100
01110
10000
10010
10100
10110
11000
11010
11100
11101
11110
11111
(1)(3)
CPU HID1
[0 – 4]
00110
00101
11000
00110
11000
00100
00100
11110
11010
11000
11010
11000
00110
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(2)
The PC8240’s internal PLLs are configured by the PLL_CFG[0–4] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the Periph-
eral Logic/Memory Bus PLL (VCO) frequency of operation for the PCI-to-Memory
frequency multiplying and the 603e CPU PLL (VCO) frequency of operation for Memory-
to-CPU frequency multiplying. The PLL configuration for the PC8240 is shown in Table
19.
(PCI_ SYNC_IN)
PCI Clock Input
Range
33
50 – 56
25 – 28
33
33
25 – 26
25 – 40
25 – 33
25 – 33
25 – 28
25 – 26
(7)
3 – 44
(8)
(8)
25
50
(1)
– 56
– 66
– 53
(MHz)
(6)
(6)
(6)
200 MHz Part
Mem Bus Clock
NOT USABLE
NOT USABLE
Periph Logic/
Range (MHz)
75 – 100
50 – 100
75 – 80
50 – 56
50 – 56
33 – 56
50 – 80
50 – 66
50 – 56
62 – 65
50 – 66
50 – 80
Bypass
Bypass
Bypass
50
50
(9)
Range (MHz)
CPU Clock
188 – 200
100 – 112
100 – 113
100 – 168
125 – 200
150 – 200
150 – 200
100 – 200
175 – 200
186 – 200
150 – 200
125 – 200
200
200
PCI to Mem
(Mem VCO)
Multiplier
Bypass
Bypass
Bypass
1.5
2.5
1.5
1.5
3
3
1
2
1
2
2
2
3
2
2
1
Off
Off
(6)
(6)
(4)
(8)
(4)
(4)
(4)
(4)
(6)
(4)
(4)
(2)
(3)
(5)
(3)
(3)
Ratios
2149A–HIREL–05/02
(4)(5)
Mem to CPU
(CPU VCO)
Multiplier
2.5
2.5
4.5
2.5
3.5
2.5
3
2
2
2
3
3
3
2
2
4
3
4
3
Off
Off
(6)
(8)
(8)
(8)
(6)
(6)
(6)
(4)
(4)
(8)
(6)
(8)
(6)
(5)
(5)
(9)
(5)
(7)
(5)