PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 23

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

PCI Signal Output Hold Timing
Table 12. Power Management Configuration Register 2-0x72
2149A–HIREL–05/02
6–4
Bit
PCI_HOLD_DEL
Name
Reset value
xx0
Figure 13. AC Test Load for the PC8240
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both
33 MHz and 66 MHz PCI systems, the PC8240 has a programmable output hold delay
for PCI signals. The initial value of the output hold delay is determined by the values on
the MCP and CKE reset configuration signals. Further output hold delay values are
available by programming the PCI_HOLD_DEL value of the PMCR2 configuration
register.
Table 12 describes the bit values for the PCI_HOLD_DEL values in PMCR2.
Description
PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5
are determined by the reset configuration pins MCP and CKE, respectively. As these two
pins have internal pull-up resistors, the default value after reset is 0b110.
While the minimum hold times are guaranteed at shown values, changes in the actual
hold time can be made by incrementing or decrementing the value in these bit fields of
this register via software or hardware configuration. The increment is in approximately
400 picosecond steps. Lowering the value in the three bit field decreases the amount of
output hold available.
000 66 MHz PCI. Pull-down MCP configuration pin with a 2K or less value
001
010
011
100 33 MHz PCI. This setting guarantees the minimum output hold,
101
110 (Default if reset configuration pins left unconnected)
111
resistor. This setting guarantees the minimum output hold, item 13a, and
the maximum output valid, item 12a, times as specified in Figure 11 are
met for a 66 MHz PCI system. See Figure 14 on page 24.
item 13a, and the maximum output valid, item 12a, times as specified in
Figure 11 are met for a 33 MHz PCI system. See Figure 14 on page 24.
OUTPUT
PIN
Z0 = 50Ω
Output measurements are made at the device pin
RL = 50Ω
OVdd/2
PC8240
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