PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 28

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 18. Two-wire Interface Timing Diagram IV (Qualified signal)
EPIC Serial Interrupt Mode AC
Timing Specifications
Table 16. EPIC Serial Interrupt Mode AC Timing Specifications
Notes:
28
Num
1
2
3
4
5
6
7
1. See the PC8240 User’s Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency
2. S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and S_CLK
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
Characteristics
S_CLK Frequency
S_CLK Duty Cycle
S_CLK Output Valid Time
Output Hold Time
S_FRAME, S_RST Output Valid
Time
S_INT Input Setup Time to S_CLK
S_INT Inputs Invalid (Hold Time) to
S_CLK
Note 1: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.
PC8240
SCL/SDAqualified
SCL/SDArealtime
programming.
and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the Motorola’s PC8240 User’s
Manual for a complete description of the functional relationships between these signals.
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See Motorola’s PC8240 User’s Manual for a complete clocking description.
Delay
(1)
VM
Table 16 provides the EPIC serial interrupt mode AC timing specifications for the
PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
VM
1 sys_logic_clk period + TBD
1/14 SDRAM_SYNC_IN
Min
40
–
0
–
–
1 sys_logic_clk period + x
1/2 SDRAM_SYNC_IN
TBD = x
Max
60
–
–
0
MHz
Unit
nS
nS
nS
nS
nS
%
2149A–HIREL–05/02
Notes
(1)
(2)
(2)
(2)