PCX8240VTPU200EZD3 Atmel, PCX8240VTPU200EZD3 Datasheet - Page 19

• Manufacturer Part Number: PCX8240VTPU200EZD3
• Description: IC MPU 32BIT 200MHZ 352TBGA
• Manufacturer: Atmel

Specifications of PCX8240VTPU200EZD3

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 9. Clock AC Timing Specifications (Continued)
Notes:
Figure 8. PCI_SYNC-IN Input Clock Timing Diagram
2149A–HIREL–05/02
Num
18
19
20
21
22
23
1. These specifications are for the default driver strengths indicated in Table 7 on page 17.
2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4V.
3. Specification value at maximum frequency of operation.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
7. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1, 2, 3, ...). T
8. Pin to pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew
Characteristics and Conditions
OSC_IN Cycle Time
OSC_IN Rise and Fall Times
OSC_IN Duty Cycle Measured at 1.4V
OSC_IN Frequency Stability
OSC_IN V
OSC_IN V
not tested.
Vdd and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been dis-
abled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted for
a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
SDRAM_SYNC_OUT clock cycle in ns. t
runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-
responds to approximately 1 ns of delay. t
DLL is contributing no delay; t
added to the clocking signals from the variable length DLL synchronization feedback loop, i.e. the amount of variance
between the internal sys-logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin to pin skew between
SDRAM_CLKs can be measured, the relationship between the internal sys-logic_clk and the external SDRAM_SYNC_IN
cannot be measured and is guaranteed by design.
PCI_SYNC_IN
IH
IL
(Loaded)
(Loaded)
VM
fix0
(1)
5a
equals approximately 3 ns. See Figure 9 on page 20 for DLL locking ranges.
1
loop
VM
fix0
is the propagation delay of the DLL synchronization feedback loop (PC board
5b
is a fixed delay inherent in the design when the DLL is at tap point 0 and the
VM = Midpoint Voltage (1.4V)
VM
CVIH
CVIL
TBD
Min
2
40
40
–
–
–
Max
TBD
100
15
60
5
clk
3
is the period of one
Unit
ppm
ns
ns
%
PC8240
V
V
Notes
(5)
19