MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 38

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

*
MOTOROLA
Function Codes
Address Bus
Data Bus
Size
*
*
Read/Write
Read-Modify-Write Cycle
Address Strobe
Data Strobe
*
Data Transfer and Size
Acknowledge
Interrupt Priority Level
*
Autovector
Bus Request
Bus Grant
*
Reset
Halt
Bus Error
Cache Disable
Clock
Power Supply
Ground
This signal is implemented in the MC68020 and not implemented in the MC68EC020.
External Cycle Start
Operand Cycle Start
Data Buffer Enable
Interrupt Pending
Bus Grant Acknowledge
MC68020
MC68EC020
Signal Name
Mnemonic
Freescale Semiconductor, Inc.
SIZ1, SIZ0
IPL2–IPL0
FC2–FC0
DSACK1,
DSACK0
A31–A0
A23–A0
D31–D0
BGACK
RESET
IPEND
AVEC
HALT
DBEN
BERR
RMC
CDIS
GND
For More Information On This Product,
OCS
CLK
V
ECS
R/ W
DS
BR
BG
AS
CC
Table 3-1. Signal Index
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M68020 USER’S MANUAL
3-bit function code used to identify the address space of each bus cycle.
32-bit address bus
24-bit address bus
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus
cycle.
Indicates the number of bytes remaining to be transferred for this cycle.
These signals, together with A1 and A0, define the active sections of the
data bus.
Provides an indication that a bus cycle is beginning.
Identical operation to that of ECS except that OCS is asserted only during
the first bus cycle of an operand transfer.
Defines the bus transfer as a processor read or write.
Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.
Indicates that a valid address is on the bus.
Indicates that valid data is to be placed on the data bus by an external
device or has been placed on the data bus by the MC68020/EC020.
Provides an enable signal for external data buffers.
Bus response signals that indicate the requested data transfer operation
has completed. In addition, these two lines indicate the size of the
external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.
Provides an encoded interrupt level to the processor.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge cycle.
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus mastership.
Indicates that an external device has assumed bus mastership.
System reset.
Indicates that the processor should suspend bus activity or that the
processor has halted due to a double bus fault.
Indicates that an erroneous bus operation is being attempted.
Statically disables the on-chip cache to assist emulator support.
Clock input to the processor.
Power supply.
Ground connection.
Function
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