MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 195

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MC68020CRC16E

Manufacturer Part Number
MC68020CRC16E
Description
IC MICROPROCESSOR 32BIT 114-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68020CRC16E

Processor Type
M680x0 32-Bit
Speed
166MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
114-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16.67MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
114
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68020CRC16E
Manufacturer:
MOT
Quantity:
10
The D/A bit specifies whether the primitive transfers an address or data register. D/A = 0
indicates a data register, and D/A = 1 indicates an address register. The register field
contains the register number.
If DR = 0, the main processor writes the long-word operand in the specified register to the
operand CIR. If DR = 1, the main processor reads a long-word operand from the operand
CIR and transfers it to the specified data or address register.
7.4.14 Transfer Main Processor Control Register Primitive
The transfer main processor control register primitive transfers a long-word operand
between one of its control registers and the coprocessor. This primitive applies to general
and conditional category instructions. Figure 7-34 shows the format of the transfer main
processor control register primitive.
The transfer main processor control register primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format. If the
coprocessor issues this primitive with CA = 0 during a conditional category instruction, the
main processor initiates protocol violation exception processing.
When the main processor receives this primitive, it reads a control register select code
from the register select CIR. This code determines which main processor control register
is transferred. Table 7-5 lists the valid control register select codes. If the control register
select code is not valid, the MC68020/EC020 initiates protocol violation exception
processing (refer to 7.5.2.1 Protocol Violations).
7-42
Figure 7-34. Transfer Main Processor Control Register Primitive Format
15
CA
PC
14
DR
13
12
All other codes cause a protocol violation exception.
0
Freescale Semiconductor, Inc.
Select Code
Table 7-5. Main Processor Control
For More Information On This Product,
11
1
$x000
$x001
$x002
$x800
$x801
$x802
$x803
$x804
10
1
Register Select Codes
M68020 USER’S MANUAL
Go to: www.freescale.com
9
0
8
1
Control Register
7
0
CACR
CAAR
MSP
SFC
DFC
USP
VBR
ISP
6
0
5
0
4
0
3
0
2
0
1
0
0
MOTOROLA
0

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