MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 189

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.4.8 Evaluate and Transfer Effective Address Primitive
The evaluate and transfer effective address primitive evaluates the effective address
specified in the coprocessor instruction operation word and transfers the result to the
coprocessor. This primitive applies to general category instructions. If this primitive is
issued by the coprocessor during the execution of a conditional category instruction, the
main processor initiates protocol violation exception processing. Figure 7-28 shows the
format of the evaluate and transfer effective address primitive.
The evaluate and transfer effective address primitive uses the CA and PC bits as
described in 7.4.2 Coprocessor Response Primitive General Format.
When the main processor reads this primitive while executing a general category
instruction, it evaluates the effective address specified in the instruction. At this point, the
scanPC contains the address of the first of any required effective address extension
words. The main processor increments the scanPC by two after it references each of
these extension words. After the effective address is calculated, the resulting 32-bit value
is written to the operand address CIR.
The MC68020/EC020 only calculates effective addresses for control alterable addressing
modes in response to this primitive. If the addressing mode in the operation word is not a
control alterable mode, the main processor aborts the instruction by writing a $0001 to the
control CIR and initiates F-line emulation exception processing (refer to 7.5.2.2 F-Line
Emulator Exceptions).
7.4.9 Evaluate Effective Address and Transfer Data Primitive
The evaluate effective address and transfer data primitive transfers an operand between
the coprocessor and the effective address specified in the coprocessor instruction
operation word. This primitive applies to general category instructions. If the coprocessor
issues this primitive during the execution of a conditional category instruction, the main
processor initiates protocol violation exception processing. Figure 7-29 shows the format
of the evaluate effective address and transfer data primitive.
This primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor
Response Primitive General Format.
7-36
Figure 7-28. Evaluate and Transfer Effective Address Primitive Format
15
CA
15
CA
PC
PC
14
14
DR
13
13
0
Figure 7-29. Evaluate Effective Address and
12
12
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
11
11
1
0
Transfer Data Primitive Format
10
10
0
M68020 USER’S MANUAL
Go to: www.freescale.com
VALID EA
9
1
9
8
8
0
7
0
7
6
0
5
0
4
0
LENGTH
3
0
2
0
1
0
MOTOROLA
0
0
0