MC68020CRC16E Freescale Semiconductor, MC68020CRC16E Datasheet - Page 149

• Manufacturer Part Number: MC68020CRC16E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bits 11–9—Reserved by Motorola
DF—Fault/Rerun Flag
RM—Read-Modify-Write
RW—Read/Write
SIZE—Size Code
Bit 3—Reserved by Motorola
FC2–FC0—Specifies the address space for data cycle
6.2.2 Using Software to Complete the Bus Cycles
One method of completing a faulted bus cycle is to use a software handler to emulate the
cycle. This is the only method for correcting address errors. The handler should emulate
the faulted bus cycle in a manner that is transparent to the instruction that caused the
fault. For instruction stream faults, the handler may need to run bus cycles for both the B
and C stages of the instruction pipe. The RB and RC bits of the SSW identify the stages
that may require a bus cycle; the FB and FC bits of the SSW indicate that a stage was
invalid when an attempt was made to use its contents. Those stages must be repaired.
For each faulted stage, the software handler should copy the instruction word from the
proper address space as indicated by the S-bit of the copy of the SR saved on the stack to
the image of the appropriate stage in the stack frame. In addition, the handler must clear
the RB or RC bit associated with the stage that it has corrected. The handler should not
change the FB and FC bits.
6-24
stack for stage B of the pipe are accepted as valid; the processor assumes that there is
no prefetch pending for stage B and that software has repaired or filled the image of
stage B, if necessary.
If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is
set when the processor reads the stack frame, it reruns the faulted data access;
otherwise, it assumes that the data input buffer value on the stack is valid for a read or
that the data has been correctly written to memory for a write (or that no data fault
occurred).
The SIZE field indicates the size of the operand access for the data cycle.
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
1 = Read-modify-write operation on data cycle
0 = Not a read-modify-write operation
1 = Read on data cycle
0 = Write on data cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
MOTOROLA