MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 624

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Serial Management Controllers (SMCs)
Bits 14, 11, 10, 8–2, 0—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
CM—Continuous Mode
The following status bit is written by the CP after the received data has been placed into the
associated data buffer.
OV—Overrun
Data Length
Rx Data Buffer Pointer
7.11.10.12 SMC TRANSPARENT TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is
presented to the CP for transmission on an SMC channel by arranging it in buffers refer-
enced by the channel’s Tx BD table. The CP confirms transmission or indicates error con-
ditions using the BDs to inform the processor that the buffers have been serviced.
7-300
A receiver overrun occurred during message reception.
The data length is the number of octets that the CP has written into this BD’s data buffer.
It is written only once by the CP as the buffer is closed.
The receive buffer pointer, which always points to the first location of the associated data
buffer, must be even. The buffer may reside in either internal or external memory.
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been filled.
1 = The RX bit in the event register will be set when this buffer has been completely
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
filled by the CP, indicating the need for the CPU32+ core to process the buffer. The
RX bit can cause an interrupt if it is enabled.
data buffer to be overwritten automatically when the CP next accesses this BD.
However, the E-bit will be cleared if an error occurs during reception, regardless of
the CM bit.
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the MRBLR.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE