MPC855TZQ80D4 Freescale Semiconductor, MPC855TZQ80D4 Datasheet - Page 36

• Manufacturer Part Number: MPC855TZQ80D4
• Description: IC MPU POWERQUICC 80MHZ 357PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICCr

Specifications of MPC855TZQ80D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 80MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 8KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 3.135V To 3.465V
• Rohs Compliant: No
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. The value of t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
8. Guaranteed by characterization.
9. Guaranteed by design.
Figure 16
36
Local bus clock to address valid for LAD
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance
for LAD/LDP
for inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1). Also, t
output (O) going invalid (X) or output hold time.
in question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
complementary signals at OV
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
provides the AC test load for the local bus.
LBOTOT
Parameter
(First two letters of functional block)(reference)(state)(signal)(state)
Table 31. Local Bus General Timing Parameters—DLL Bypassed (continued)
LBKHOX
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
Output
symbolizes local bus timing (LB) for the t
DD
/2.
DD
/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV
Figure 16. Local Bus C Test Load
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
Z
Configuration
LWE[0:1] = 00
LWE[0:1] = 00
LWE[0:1] = 00
LWE[0:1] = 00
LWE[0:1] = 00
0
= 50 Ω
7
LBK
Symbol
for outputs. For example, t
t
t
t
t
t
LBKLOV3
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
(First two letters of functional block)(signal)(state) (reference)(state)
LBK
clock reference (K) to go high (H), with respect to the
R
clock reference (K) goes high (H), in this case for
L
1
= 50 Ω
–2.7
–1.8
–2.7
–1.8
Min
—
—
—
OV
DD
Max
0.8
2.3
1.0
2.4
1.0
2.4
/2
—
—
LBIXKH1
Freescale Semiconductor
symbolizes local bus
Unit
ns
ns
ns
ns
ns
DD
of the signal
Notes
3
3
3
5
5