MPC855TZQ80D4 Freescale Semiconductor, MPC855TZQ80D4 Datasheet - Page 35

• Manufacturer Part Number: MPC855TZQ80D4
• Description: IC MPU POWERQUICC 80MHZ 357PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICCr

Specifications of MPC855TZQ80D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 80MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 8KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 3.135V To 3.465V
• Rohs Compliant: No
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 31
bypassed.
Freescale Semiconductor
Local bus clock to output high impedance for
LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. The value of t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
8. Guaranteed by characterization.
9. Guaranteed by design.
Local bus cycle time
Internal launch/capture clock to LCLK
delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
(reference)(state)
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
high (H), in this case for clock one(1). Also, t
high (H), with respect to the output (O) going invalid (X) or output hold time.
question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
complementary signals at OV
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
Parameter
LBOTOT
Parameter
for inputs and t
Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of
Table 31. Local Bus General Timing Parameters—DLL Bypassed
(First two letters of functional block)(reference)(state)(signal)(state)
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LBKHOX
Configuration
Configuration
LWE[0:1] = 00
LWE[0:1] = 00
LWE[0:1] = 00
symbolizes local bus timing (LB) for the t
7
7
Symbol
t
t
t
LBKSKEW
t
t
t
t
Symbol
t
t
LBKLOV1
LBKLOV2
t
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBKHKT
LBOTOT
LBKHOZ2
t
(First two letters of functional block)(signal)(state)
LBK
1
1
–1.3
–0.8
Min
6.0
1.8
5.2
5.1
1.5
—
—
—
Min
for outputs. For example, t
—
LBK
LBK
Max
150
3.4
0.5
2.0
0.7
2.2
Max
—
—
—
—
—
—
2.8
4.2
clock reference (K) to go
clock reference (K) goes
DD
of the signal in
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
Unit
ns
LBIXKH1
Local Bus
Notes
Notes
7, 9
3, 4
3, 4
3, 4
3, 4
5, 9
2
8
6
3
3
35