KU80960CA25 Intel, KU80960CA25 Datasheet - Page 5

• Manufacturer Part Number: KU80960CA25
• Description: IC MPU I960CA 5V 25MHZ 196QFP
• Manufacturer: Intel

Specifications of KU80960CA25

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: CA suffix, 32-Bit with DMA
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 196-QFP
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 802900

1.0
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic—other than parametric performance—consult
the 80960CA Product Overview (Order No. 270669)
or the i960
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel’s FaxBACK
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600).
2.0
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
PURPOSE
80960CA OVERVIEW
Interrupt
Port
CA Microprocessor User’s Manual
Interrupt Controller
Multiply/Divide
Programmable
Execution
Unit
Unit
Figure 1. 80960CA Block Diagram
Register-side
Machine Bus
Instruction Prefetch Queue
64-Bit
SRC2 Bus
64-Bit
SRC1 Bus
64-Bit
DST Bus
128-BIT CACHE BUS
data-on-
(1 KByte, Two-way
Instruction Cache
Set Associative)
Register File
Instruction
Scheduler
Six-port
Parallel
Memory-side
Machine Bus
Store Bus
Base Bus
Load Bus
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system’s
high-speed
addition, the 80960CA’s on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system’s
slower, cost sensitive, main memory subsystem.
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers—in
addition to source or destination synchronized trans-
fers—are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (”latency”) time of
750 ns.
128-Bit
128-Bit
32-Bit
external
Generation Unit
Memory Region
Register Cache
DMA Controller
Bus Request
Four-Channel
Configuration
5 to 15 Sets
Data RAM
Address
Queues
1 KByte
Controller
Bus
memory
80960CA-33, -25, -16
Control
Address
DMA
Port
Data
sub-system.
F_CX001A
In
1